1 /** @file dma.h 2 * @brief DMA Driver Definition File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 */ 7 8 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 9 10 #ifndef __DMA_H__ 11 #define __DMA_H__ 12 13 #include "reg_dma.h" 14 15 /* dma configuration definitions */ 16 17 #define BLOCK_TRANSFER 1U 18 #define FRAME_TRANSFER 0U 19 20 #define AUTOINIT_ON 1U 21 #define AUTOINIT_OFF 0U 22 23 #define ADDR_FIXED 0U 24 #define ADDR_INC1 1U 25 #define ADDR_RESERVED 2U 26 #define ADDR_OFFSET 3U 27 28 #define INTERRUPT_ENABLE 1U 29 #define INTERRUPT_DISABLE 0U 30 31 32 /*Bit Masks*/ 33 #define DMA_GCTRL_BUSBUSY (1U << 14U) 34 /** @enum dmaREQTYPE 35 * @brief DMA TRANSFER Type definitions 36 * 37 * Used to define DMA transfer type 38 */ 39 enum dmaREQTYPE 40 { 41 DMA_HW = 0x0U, /**< Hardware trigger */ 42 DMA_SW = 0x1U /**< Software trigger */ 43 }; 44 45 46 /** @enum dmaCHANNEL 47 * @brief DMA CHANNEL definitions 48 * 49 * Used to define DMA Channel Number 50 */ 51 enum dmaCHANNEL 52 { 53 DMA_CH0 = 0x00U, 54 DMA_CH1 = 0x01U, 55 DMA_CH2 = 0x02U, 56 DMA_CH3 = 0x03U, 57 DMA_CH4 = 0x04U, 58 DMA_CH5 = 0x05U, 59 DMA_CH6 = 0x06U, 60 DMA_CH7 = 0x07U, 61 DMA_CH8 = 0x08U, 62 DMA_CH9 = 0x09U, 63 DMA_CH10 = 0x0AU, 64 DMA_CH11 = 0x0BU, 65 DMA_CH12 = 0x0CU, 66 DMA_CH13 = 0x0DU, 67 DMA_CH14 = 0x0EU, 68 DMA_CH15 = 0x0FU, 69 DMA_CH16 = 0x10U, 70 DMA_CH17 = 0x11U, 71 DMA_CH18 = 0x12U, 72 DMA_CH19 = 0x13U, 73 DMA_CH20 = 0x14U, 74 DMA_CH21 = 0x15U, 75 DMA_CH22 = 0x16U, 76 DMA_CH23 = 0x17U, 77 DMA_CH24 = 0x18U, 78 DMA_CH25 = 0x19U, 79 DMA_CH26 = 0x1AU, 80 DMA_CH27 = 0x1BU, 81 DMA_CH28 = 0x1CU, 82 DMA_CH29 = 0x1DU, 83 DMA_CH30 = 0x1EU, 84 DMA_CH31 = 0x1FU, 85 DMA_CH32 = 0x20U 86 }; 87 88 /** @enum dmaACCESS 89 * @brief DMA ACESS WIDTH definitions 90 * 91 * Used to define DMA access width 92 */ 93 typedef enum dmaACCESS 94 { 95 ACCESS_8_BIT = 0U, 96 ACCESS_16_BIT = 1U, 97 ACCESS_32_BIT = 2U, 98 ACCESS_64_BIT = 3U 99 }dmaACCESS_t; 100 101 102 /** @enum dmaPRIORITY 103 * @brief DMA Channel Priority 104 * 105 * Used to define to which priority queue a DMA channel is assigned to 106 */ 107 typedef enum dmaPRIORITY 108 { 109 LOWPRIORITY = 0U, 110 HIGHPRIORITY = 1U 111 }dmaPRIORITY_t; 112 113 114 /** @enum dmaREGION 115 * @brief DMA Memory Protection Region 116 * 117 * Used to define DMA Memory Protection Region 118 */ 119 typedef enum dmaREGION 120 { 121 DMA_REGION0 = 0U, 122 DMA_REGION1 = 1U, 123 DMA_REGION2 = 2U, 124 DMA_REGION3 = 3U 125 }dmaREGION_t; 126 127 128 /** @enum dmaRegionAccess 129 * @brief DMA Memory Protection Region Access 130 * 131 * Used to define access permission of DMA memory protection regions 132 */ 133 typedef enum dmaRegionAccess 134 { 135 FULLACCESS = 0U, 136 READONLY = 1U, 137 WRITEONLY = 2U, 138 NOACCESS = 3U 139 }dmaRegionAccess_t; 140 141 142 /** @enum dmaInterrupt 143 * @brief DMA Interrupt 144 * 145 * Used to define DMA interrupts 146 */ 147 typedef enum dmaInterrupt 148 { 149 FTC = 1U, /**< Frame transfer complete Interrupt */ 150 LFS = 2U, /**< Last frame transfer started Interrupt */ 151 HBC = 3U, /**< First half of block complete Interrupt */ 152 BTC = 4U /**< Block transfer complete Interrupt */ 153 }dmaInterrupt_t; 154 155 /** @struct g_dmaCTRL 156 * @brief Interrupt mode globals 157 * 158 */ 159 typedef struct dmaCTRLPKT 160 { 161 uint32 SADD; /* initial source address */ 162 uint32 DADD; /* initial destination address */ 163 uint32 CHCTRL; /* channel count */ 164 uint32 FRCNT; /* frame count */ 165 uint32 ELCNT; /* element count */ 166 uint32 ELDOFFSET; /* element destination offset */ 167 uint32 ELSOFFSET; /* element source offset */ 168 uint32 FRDOFFSET; /* frame detination offset */ 169 uint32 FRSOFFSET; /* frame source offset */ 170 uint32 PORTASGN; /* dma port */ 171 uint32 RDSIZE; /* read element size */ 172 uint32 WRSIZE; /* write element size */ 173 uint32 TTYPE; /* trigger type - frame/block */ 174 uint32 ADDMODERD; /* addresssing mode for source */ 175 uint32 ADDMODEWR; /* addresssing mode for destination */ 176 uint32 AUTOINIT; /* auto-init mode */ 177 uint32 COMBO; /* next ctrl packet trigger */ 178 } g_dmaCTRL; 179 180 typedef volatile struct 181 { 182 183 struct /* 0x000-0x400 */ 184 { 185 uint32 ISADDR; 186 uint32 IDADDR; 187 uint32 ITCOUNT; 188 uint32 rsvd1; 189 uint32 CHCTRL; 190 uint32 EIOFF; 191 uint32 FIOFF; 192 uint32 rsvd2; 193 }PCP[32U]; 194 195 struct /* 0x400-0x800 */ 196 { 197 uint32 res[256U]; 198 } RESERVED; 199 200 struct /* 0x800-0xA00 */ 201 { 202 uint32 CSADDR; 203 uint32 CDADDR; 204 uint32 CTCOUNT; 205 uint32 rsvd3; 206 }WCP[32U]; 207 208 } dmaRAMBASE_t; 209 210 #define dmaRAMREG ((dmaRAMBASE_t *)0xFFF80000U) 211 212 /** 213 * @defgroup DMA DMA 214 * @brief Direct Memory Access Controller 215 * 216 * The DMA controller is used to transfer data between two locations in the memory map in the background 217 * of CPU operations. Typically, the DMA is used to: 218 * - Transfer blocks of data between external and internal data memories 219 * - Restructure portions of internal data memory 220 * - Continually service a peripheral 221 * - Page program sections to internal program memory 222 * 223 * Related files: 224 * - reg_dma.h 225 * - sys_dma.h 226 * - sys_dma.c 227 * 228 * @addtogroup DMA 229 * @{ 230 */ 231 /* DMA Interface Functions */ 232 void dmaEnable(void); 233 void dmaDisable(void); 234 void dmaSetCtrlPacket(uint32 channel, g_dmaCTRL g_dmaCTRLPKT); 235 void dmaSetChEnable(uint32 channel,uint32 type); 236 void dmaReqAssign(uint32 channel,uint32 reqline); 237 uint32 dmaGetReq(uint32 channel); 238 void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority); 239 void dmaEnableInterrupt(uint32 channel, dmaInterrupt_t inttype); 240 void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype); 241 void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add); 242 void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, boolean intenable); 243 void dmaDisableRegion(dmaREGION_t region); 244 void dmaEnableParityCheck(void); 245 void dmaDisableParityCheck(void); 246 /** @fn void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel) 247 * @brief Interrupt callback 248 * @param[in] inttype Interrupt type 249 * - FTC 250 * - LFS 251 * - HBC 252 * - BTC 253 * @param[in] channel channel number 0..15 254 * This is a callback that is provided by the application and is called apon 255 * an interrupt. The parameter passed to the callback is a copy of the 256 * interrupt flag register. 257 */ 258 void dmaGroupANotification(dmaInterrupt_t inttype, sint32 channel); 259 260 /**@}*/ 261 #endif 262