1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the People's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY'S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS'SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY'S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef __DMA_SUN50IW11_H__ 34 #define __DMA_SUN50IW11_H__ 35 36 #if defined(CONFIG_CORE_DSP0) 37 #include <hal_prcm.h> 38 39 #define SUNXI_DMAC_PBASE (0x07091000) 40 #define DMA_IRQ_NUM (6) 41 42 #define NR_MAX_CHAN 8 /* total of channels */ 43 #define START_CHAN_OFFSET 0 44 45 #define HAL_CLK_PERIPH_DMA CCU_MOD_CLK_R_DMA 46 #else 47 /* CPUX */ 48 #endif /* CONFIG_CORE_DSP0 */ 49 50 /* 51 * The source DRQ type and port corresponding relation 52 */ 53 #define DRQSRC_SRAM 0 54 #define DRQSRC_PSRAM_CBUS 0 55 #define DRQSRC_SDRAM 0 56 /* #define DRQSRC_RESEVER 2 */ 57 #define DRQSRC_DAUDIO_0_RX 3 58 #define DRQSRC_DAUDIO_1_RX 4 59 #define DRQSRC_UART0_RX 5 60 /* #define DRQSRC_RESEVER 6 */ 61 #define DRQSRC_TWI0_RX 7 62 #define DRQSRC_DMIC 8 63 #define DRQSRC_AUDIO_CODEC 9 64 /* #define DRQSRC_RESEVER 10 */ 65 #define DRQSRC_MAD_RX 11 66 #define DRQSRC_PSRAM_SBUS 12 67 68 /* 69 * The destination DRQ type and port corresponding relation 70 */ 71 #define DRQDST_SRAM 0 72 #define DRQDST_PSRAM_CBUS 0 73 #define DRQDST_SDRAM 0 74 /* #define DRQDST_RESEVER 2 */ 75 #define DRQDST_DAUDIO_0_TX 3 76 #define DRQDST_DAUDIO_1_TX 4 77 #define DRQDST_UART0_TX 5 78 /* #define DRQDST_RESEVER 6 */ 79 #define DRQDST_TWI0_TX 7 80 /* #define DRQDST_RESEVER 8 */ 81 #define DRQDST_AUDIO_CODEC 9 82 /* #define DRQDST_RESEVER 10 */ 83 #define DRQDST_MAD_TX 11 84 #define DRQDST_PSRAM_SBUS 12 85 86 #endif /*__DMA_SUN50IW11_H__ */ 87