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Searched refs:DRVCTRL (Results 1 – 22 of 22) sorted by relevance

/bsp/microchip/samc21/bsp/hri/
A Dhri_tcc_c21.h3032 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE0_bit()
3041 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE0_bit()
3044 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE0_bit()
3072 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE1_bit()
3081 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE1_bit()
3084 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE1_bit()
3112 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE2_bit()
3121 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE2_bit()
3124 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE2_bit()
3152 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE3_bit()
[all …]
A Dhri_tc_c21.h1456 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_INVEN0_bit()
1465 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_write_DRVCTRL_INVEN0_bit()
1468 ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; in hri_tc_write_DRVCTRL_INVEN0_bit()
1496 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_INVEN1_bit()
1505 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_write_DRVCTRL_INVEN1_bit()
1508 ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; in hri_tc_write_DRVCTRL_INVEN1_bit()
1529 ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; in hri_tc_set_DRVCTRL_reg()
1536 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_reg()
1544 ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; in hri_tc_write_DRVCTRL_reg()
1558 ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; in hri_tc_toggle_DRVCTRL_reg()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_tcc_d51.h3218 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE0_bit()
3227 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE0_bit()
3230 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE0_bit()
3258 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE1_bit()
3267 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE1_bit()
3270 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE1_bit()
3298 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE2_bit()
3307 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE2_bit()
3310 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE2_bit()
3338 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE3_bit()
[all …]
A Dhri_tc_d51.h1560 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_INVEN0_bit()
1569 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_write_DRVCTRL_INVEN0_bit()
1572 ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; in hri_tc_write_DRVCTRL_INVEN0_bit()
1600 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_INVEN1_bit()
1609 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_write_DRVCTRL_INVEN1_bit()
1612 ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; in hri_tc_write_DRVCTRL_INVEN1_bit()
1633 ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; in hri_tc_set_DRVCTRL_reg()
1640 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_reg()
1648 ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; in hri_tc_write_DRVCTRL_reg()
1662 ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; in hri_tc_toggle_DRVCTRL_reg()
[all …]
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_tcc_d51.h3218 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE0_bit()
3227 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE0_bit()
3230 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE0_bit()
3258 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE1_bit()
3267 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE1_bit()
3270 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE1_bit()
3298 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE2_bit()
3307 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE2_bit()
3310 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE2_bit()
3338 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE3_bit()
[all …]
A Dhri_tc_d51.h1560 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_INVEN0_bit()
1569 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_write_DRVCTRL_INVEN0_bit()
1572 ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; in hri_tc_write_DRVCTRL_INVEN0_bit()
1600 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_INVEN1_bit()
1609 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_write_DRVCTRL_INVEN1_bit()
1612 ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; in hri_tc_write_DRVCTRL_INVEN1_bit()
1633 ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; in hri_tc_set_DRVCTRL_reg()
1640 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_reg()
1648 ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; in hri_tc_write_DRVCTRL_reg()
1662 ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; in hri_tc_toggle_DRVCTRL_reg()
[all …]
/bsp/microchip/same54/bsp/hri/
A Dhri_tcc_e54.h3218 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE0_bit()
3227 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE0_bit()
3230 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE0_bit()
3258 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE1_bit()
3267 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE1_bit()
3270 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE1_bit()
3298 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE2_bit()
3307 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_write_DRVCTRL_NRE2_bit()
3310 ((Tcc *)hw)->DRVCTRL.reg = tmp; in hri_tcc_write_DRVCTRL_NRE2_bit()
3338 tmp = ((Tcc *)hw)->DRVCTRL.reg; in hri_tcc_get_DRVCTRL_NRE3_bit()
[all …]
A Dhri_tc_e54.h1560 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_INVEN0_bit()
1569 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_write_DRVCTRL_INVEN0_bit()
1572 ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; in hri_tc_write_DRVCTRL_INVEN0_bit()
1600 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_INVEN1_bit()
1609 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_write_DRVCTRL_INVEN1_bit()
1612 ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; in hri_tc_write_DRVCTRL_INVEN1_bit()
1633 ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; in hri_tc_set_DRVCTRL_reg()
1640 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_reg()
1648 ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; in hri_tc_write_DRVCTRL_reg()
1662 ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; in hri_tc_toggle_DRVCTRL_reg()
[all …]
/bsp/microchip/saml10/bsp/hri/
A Dhri_tc_l10.h1564 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_INVEN0_bit()
1573 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_write_DRVCTRL_INVEN0_bit()
1576 ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; in hri_tc_write_DRVCTRL_INVEN0_bit()
1604 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_INVEN1_bit()
1613 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_write_DRVCTRL_INVEN1_bit()
1616 ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; in hri_tc_write_DRVCTRL_INVEN1_bit()
1637 ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; in hri_tc_set_DRVCTRL_reg()
1644 tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; in hri_tc_get_DRVCTRL_reg()
1652 ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; in hri_tc_write_DRVCTRL_reg()
1666 ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; in hri_tc_toggle_DRVCTRL_reg()
[all …]
/bsp/microchip/samc21/bsp/samc21/include/component/
A Dtc.h757 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
783 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
807 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
A Dtcc.h1677 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ member
/bsp/microchip/same54/bsp/include/component/
A Dtc.h779 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
805 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
829 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
A Dtcc.h1737 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dtc.h779 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
805 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
829 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
A Dtcc.h1737 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ member
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dtc.h779 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
805 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
829 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ member
A Dtcc.h1737 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ member
/bsp/microchip/saml10/bsp/include/component/
A Dtc.h956 __IO TC_DRVCTRL_Type DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */ member
980 __IO TC_DRVCTRL_Type DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */ member
1004 __IO TC_DRVCTRL_Type DRVCTRL; /**< Offset: 0x0D (R/W 8) Control C */ member
/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_l_c/
A Dtc.c300 hw->COUNT8.DRVCTRL.reg = config->waveform_invert_output; in tc_init()
/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/
A Dtcc.c638 hw->DRVCTRL.reg = drvctrl; in tcc_init()
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/
A Dtcc.h1812 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ member
A Dtcc_lighting.h1812 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ member

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