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Searched refs:Divider (Results 1 – 22 of 22) sorted by relevance

/bsp/frdm-k64f/device/
A Dsystem_MK64F12.c149 uint16_t Divider; in SystemCoreClockUpdate() local
172 Divider = 1536U; in SystemCoreClockUpdate()
175 Divider = 1280U; in SystemCoreClockUpdate()
178 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
182 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); in SystemCoreClockUpdate()
184 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ in SystemCoreClockUpdate()
219 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
220 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ in SystemCoreClockUpdate()
221 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
222 MCGOUTClock *= Divider; /* Calculate the MCG output clock */ in SystemCoreClockUpdate()
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/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Source/
A Dlib_clk.c208 assert_parameters(IS_CLK_RTCDIV(CLK_ClkInitStruct->RTCCLK.Divider)); in CLK_ClockConfig()
217 RTC_PrescalerConfig(CLK_ClkInitStruct->RTCCLK.Divider); in CLK_ClockConfig()
277 assert_parameters(IS_CLK_HCLKDIV(CLK_ClkInitStruct->HCLK.Divider)); in CLK_ClockConfig()
279 MISC2->CLKDIVH = (CLK_ClkInitStruct->HCLK.Divider) - 1; in CLK_ClockConfig()
285 assert_parameters(IS_CLK_PCLKDIV(CLK_ClkInitStruct->PCLK.Divider)); in CLK_ClockConfig()
287 MISC2->CLKDIVP = (CLK_ClkInitStruct->PCLK.Divider) - 1; in CLK_ClockConfig()
616 CLK_ClkInitStruct->HCLK.Divider = (uint32_t)((MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1); in CLK_GetClockConfig()
618 CLK_ClkInitStruct->PCLK.Divider = (uint32_t)((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1); in CLK_GetClockConfig()
A Dlib_gpio.c446 void GPIO_PLLDIVConfig(uint32_t Divider) in GPIO_PLLDIVConfig() argument
451 assert_parameters(IS_GPIO_PLLDIV(Divider)); in GPIO_PLLDIVConfig()
455 tmp |= Divider; in GPIO_PLLDIVConfig()
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Source/
A Dlib_clk.c220 assert_parameters(IS_CLK_RTCDIV(CLK_ClkInitStruct->RTCCLK.Divider)); in CLK_ClockConfig()
229 RTC_PrescalerConfig(CLK_ClkInitStruct->RTCCLK.Divider); in CLK_ClockConfig()
292 assert_parameters(IS_CLK_HCLKDIV(CLK_ClkInitStruct->HCLK.Divider)); in CLK_ClockConfig()
294 MISC2->CLKDIVH = (CLK_ClkInitStruct->HCLK.Divider) - 1; in CLK_ClockConfig()
300 assert_parameters(IS_CLK_PCLKDIV(CLK_ClkInitStruct->PCLK.Divider)); in CLK_ClockConfig()
302 MISC2->CLKDIVP = (CLK_ClkInitStruct->PCLK.Divider) - 1; in CLK_ClockConfig()
576 CLK_ClkInitStruct->HCLK.Divider = (uint32_t)((MISC2->CLKDIVH & MISC2_CLKDIVH_CLKDIVH) + 1); in CLK_GetClockConfig()
578 CLK_ClkInitStruct->PCLK.Divider = (uint32_t)((MISC2->CLKDIVP & MISC2_CLKDIVP_CLKDIVP) + 1); in CLK_GetClockConfig()
A Dlib_gpio.c519 void GPIO_PLLDIV_Config(uint32_t Divider) in GPIO_PLLDIV_Config() argument
524 assert_parameters(IS_GPIO_PLLDIV(Divider)); in GPIO_PLLDIV_Config()
528 tmp |= Divider; in GPIO_PLLDIV_Config()
/bsp/Vango/v85xxp/drivers/
A Dboard.c39 CLK_Struct.HCLK.Divider = 1; in SystemClock_Config()
40 CLK_Struct.PCLK.Divider = 2; in SystemClock_Config()
/bsp/Vango/v85xx/drivers/
A Dboard.c39 CLK_Struct.HCLK.Divider = 1; in SystemClock_Config()
40 CLK_Struct.PCLK.Divider = 2; in SystemClock_Config()
/bsp/Vango/v85xx/Libraries/VangoV85xx_standard_peripheral/Include/
A Dlib_clk.h54 uint32_t Divider; member
60 uint32_t Divider; /* 1 ~ 256 */ member
66 uint32_t Divider; /* 1 ~ 256 */ member
A Dlib_gpio.h166 void GPIO_PLLDIV_Config(uint32_t Divider);
/bsp/Vango/v85xxp/Libraries/VangoV85xxP_standard_peripheral/Include/
A Dlib_clk.h54 uint32_t Divider; member
60 uint32_t Divider; /* 1 ~ 256 */ member
66 uint32_t Divider; /* 1 ~ 256 */ member
A Dlib_gpio.h216 void GPIO_PLLDIVConfig(uint32_t Divider);
/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/src/
A Dn32l43x_lcd.c80 assert_param(IS_LCD_DIVIDER(LCD_InitStructure->Divider)); in LCD_Init()
117 tmp |= LCD_InitStructure->Divider; in LCD_Init()
/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/src/
A Dn32l40x_lcd.c80 assert_param(IS_LCD_DIVIDER(LCD_InitStructure->Divider)); in LCD_Init()
117 tmp |= LCD_InitStructure->Divider; in LCD_Init()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/
A Dsystem_RV32M1_ri5cy.c391 uint16_t Divider; in SystemCoreClockUpdate() local
392 Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1; in SystemCoreClockUpdate()
414 SystemCoreClock = (SCGOUTClock / Divider); in SystemCoreClockUpdate()
A Dsystem_RV32M1_zero_riscy.c394 uint16_t Divider; in SystemCoreClockUpdate() local
395 Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1; in SystemCoreClockUpdate()
417 SystemCoreClock = (SCGOUTClock / Divider); in SystemCoreClockUpdate()
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_hal_lcd.c191 assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider)); in HAL_LCD_Init()
238 … (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \ in HAL_LCD_Init()
/bsp/stm32/stm32mp157a-st-ev1/board/ports/
A Ddrv_dfsdm.c119 hdfsdm1_channel1.Init.OutputClock.Divider = 74; /* 209/74 = 2.82MHZ*/ in rt_hw_dfsdm_init()
139 hdfsdm1_channel0.Init.OutputClock.Divider = 74; /* 209/74 = 2.82MHZ*/ in rt_hw_dfsdm_init()
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_hal_lcd.h57 uint32_t Divider; /*!< Configures the LCD Divider. member
/bsp/n32/libraries/N32L40x_Firmware_Library/n32l40x_std_periph_driver/inc/
A Dn32l40x_lcd.h664 uint32_t Divider; /*!< Configures the LCD Divider. member
/bsp/n32/libraries/N32L43x_Firmware_Library/n32l43x_std_periph_driver/inc/
A Dn32l43x_lcd.h664 uint32_t Divider; /*!< Configures the LCD Divider. member
/bsp/stm32/stm32l496-st-discovery/board/CubeMX_Config/Src/
A Dmain.c497 hdfsdm1_channel1.Init.OutputClock.Divider = 2; in MX_DFSDM1_Init()
514 hdfsdm1_channel2.Init.OutputClock.Divider = 2; in MX_DFSDM1_Init()
/bsp/microchip/same70/bsp/
A Datmel_start_config.atstart201 _$freq_output_UDPLL with Divider (MCKR UPLLDIV2): 240000000
226 clk_gen_pck5_oscillator: UDPLL with Divider (MCKR UPLLDIV2)

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