| /bsp/xuantie/xiaohui/r910/ |
| A D | README.md | 25 • 指令紧耦合内存大小可配置，支持 16KB、32KB、64KB，可配置 ECC 校验；
27 • 数据紧耦合内存大小可配置，支持 16KB、32KB、64KB，可配置 ECC 校验；
31 • 指令高缓可配置奇偶校验，数据高缓可配置 ECC 校验；
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| /bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | startup_cm0plus.s | 106 …; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 co…
107 …_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC h…
109 … or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
125 …; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 b…
126 …; because the ECC initialization feature uses this generic granularity that will cover any memory …
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| /bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | startup_cm0plus.s | 106 …; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 co…
107 …_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC h…
109 … or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
125 …; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 b…
126 …; because the ECC initialization feature uses this generic granularity that will cover any memory …
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| /bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/TOOLCHAIN_ARM/ |
| A D | startup_cm0plus.s | 106 …; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 co…
107 …_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC h…
109 … or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
125 …; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 b…
126 …; because the ECC initialization feature uses this generic granularity that will cover any memory …
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| /bsp/microchip/same54/ |
| A D | README_zh.md | 18 - Error Correction Code (ECC)
22 - 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option
88 - RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)
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| A D | README.md | 18 - Error Correction Code (ECC)
22 - 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option
88 - RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)
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| /bsp/microchip/samd51-adafruit-metro-m4/ |
| A D | README_zh.md | 21 - Error Correction Code (ECC)
25 - 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option
95 - RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)
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| A D | README.md | 21 - Error Correction Code (ECC)
25 - 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option
95 - RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)
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| /bsp/microchip/samd51-seeed-wio-terminal/ |
| A D | README.md | 23 - Error Correction Code (ECC)
28 - 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option
98 - RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)
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| A D | README_zh.md | 23 - Error Correction Code (ECC)
28 - 64 KB, 96 KB, 128 KB of Error Correction Code (ECC) RAM option
98 - RSA, DSA : Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)
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| /bsp/Infineon/libraries/templates/XMC7200D/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/TOOLCHAIN_IAR/ |
| A D | startup_cm0plus.s | 169 ; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
170 …_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC h…
172 ; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
188 ; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 by…
189 ; because the ECC initialization feature uses this generic granularity that will cover any memory (…
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| /bsp/Infineon/xmc7100d-f144k4160aa/libs/TARGET_APP_KIT_XMC71_EVK_LITE_V2/COMPONENT_CM0P/TOOLCHAIN_IAR/ |
| A D | startup_cm0plus.s | 169 ; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
170 …_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC h…
172 ; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
188 ; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 by…
189 ; because the ECC initialization feature uses this generic granularity that will cover any memory (…
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| /bsp/Infineon/xmc7200-kit_xmc7200_evk/libs/TARGET_APP_KIT_XMC72_EVK/COMPONENT_CM0P/TOOLCHAIN_IAR/ |
| A D | startup_cm0plus.s | 169 ; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
170 …_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC h…
172 ; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
188 ; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 by…
189 ; because the ECC initialization feature uses this generic granularity that will cover any memory (…
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| /bsp/yichip/yc3121-pos/ |
| A D | README.md | 40 - 非对称算法：RSA-1024/2048、国密II（SM2）、ECC
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| /bsp/yichip/yc3122-pos/ |
| A D | README.md | 45 - 非对称算法：RSA-1024/2048、国密II（SM2）、ECC
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| /bsp/renesas/ra6m3-hmi-board/script/ |
| A D | fsp.scat | 398 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
409 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
435 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
446 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
461 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
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| /bsp/renesas/ra4e2-eco/script/ |
| A D | fsp.scat | 413 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
424 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
450 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
461 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
476 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
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| /bsp/renesas/ra6e2-fpb/script/ |
| A D | fsp.scat | 402 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
413 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
439 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
450 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
465 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
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| /bsp/hpmicro/libraries/hpm_sdk/drivers/inc/ |
| A D | hpm_bkey_drv.h | 83 ptr->ECC[key] = BKEY_ECC_ECC_SET(ecc) | lock; in bkey_lock()
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/ |
| A D | hpm_bkey_regs.h | 16 __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ member
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/ |
| A D | hpm_bkey_regs.h | 16 __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ member
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/ |
| A D | hpm_bkey_regs.h | 16 __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ member
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/ |
| A D | hpm_bkey_regs.h | 16 __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ member
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| /bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/ |
| A D | hpm_bkey_regs.h | 16 __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ member
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| /bsp/renesas/ra8d1-ek/script/ |
| A D | fsp.scat | 416 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
427 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
453 ; The required minimum execution address alignment is an 8 byte boundary for ECC compatibility.
464 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
479 ; The required minimum ending alignment is an 8 byte boundary for ECC compatibility.
|