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Searched refs:EIC_CONFIG_FILTEN5 (Results 1 – 11 of 11) sorted by relevance

/bsp/microchip/samc21/bsp/hri/
A Dhri_eic_c21.h907 ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; in hri_eic_set_CONFIG_FILTEN5_bit()
915 tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; in hri_eic_get_CONFIG_FILTEN5_bit()
924 tmp &= ~EIC_CONFIG_FILTEN5; in hri_eic_write_CONFIG_FILTEN5_bit()
933 ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; in hri_eic_clear_CONFIG_FILTEN5_bit()
940 ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; in hri_eic_toggle_CONFIG_FILTEN5_bit()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_eic_d51.h933 ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; in hri_eic_set_CONFIG_FILTEN5_bit()
941 tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; in hri_eic_get_CONFIG_FILTEN5_bit()
950 tmp &= ~EIC_CONFIG_FILTEN5; in hri_eic_write_CONFIG_FILTEN5_bit()
959 ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; in hri_eic_clear_CONFIG_FILTEN5_bit()
966 ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; in hri_eic_toggle_CONFIG_FILTEN5_bit()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_eic_d51.h933 ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; in hri_eic_set_CONFIG_FILTEN5_bit()
941 tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; in hri_eic_get_CONFIG_FILTEN5_bit()
950 tmp &= ~EIC_CONFIG_FILTEN5; in hri_eic_write_CONFIG_FILTEN5_bit()
959 ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; in hri_eic_clear_CONFIG_FILTEN5_bit()
966 ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; in hri_eic_toggle_CONFIG_FILTEN5_bit()
/bsp/microchip/same54/bsp/hri/
A Dhri_eic_e54.h933 ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; in hri_eic_set_CONFIG_FILTEN5_bit()
941 tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; in hri_eic_get_CONFIG_FILTEN5_bit()
950 tmp &= ~EIC_CONFIG_FILTEN5; in hri_eic_write_CONFIG_FILTEN5_bit()
959 ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; in hri_eic_clear_CONFIG_FILTEN5_bit()
966 ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; in hri_eic_toggle_CONFIG_FILTEN5_bit()
/bsp/microchip/samc21/bsp/samc21/include/component/
A Deic.h367 #define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos) macro
/bsp/microchip/same54/bsp/include/component/
A Deic.h367 #define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos) macro
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Deic.h367 #define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos) macro
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Deic.h367 #define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos) macro
/bsp/microchip/saml10/bsp/include/component/
A Deic.h414 #define EIC_CONFIG_FILTEN5 EIC_CONFIG_FILTEN5_Msk /**< \de… macro
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/
A Deic.h629 #define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos) macro
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/
A Deic.h626 #define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos) macro

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