1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2013-01-30 weety first version 9 */ 10 11 #ifndef _DAVINCI_EMAC_H 12 #define _DAVINCI_EMAC_H 13 #include <mii.h> 14 15 #ifndef NET_IP_ALIGN 16 #define NET_IP_ALIGN 2 17 #endif 18 19 enum { 20 EMAC_VERSION_1, /* DM644x */ 21 EMAC_VERSION_2, /* DM646x */ 22 }; 23 24 25 #define __iomem 26 27 #define BIT(nr) (1UL << (nr)) 28 29 30 /* Configuration items */ 31 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC upto frames */ 32 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ 33 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ 34 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ 35 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ 36 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ 37 #define EMAC_DEF_PROM_EN (0) /* Promiscous disabled */ 38 #define EMAC_DEF_PROM_CH (0) /* Promiscous channel is 0 */ 39 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ 40 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ 41 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ 42 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ 43 44 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ 45 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ 46 47 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ 48 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ 49 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) 50 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */ 51 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */ 52 #define EMAC_DEF_MDIO_TICK_MS (10) /* typically 1 tick=1 ms) */ 53 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ 54 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ 55 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ 56 57 /* Buffer descriptor parameters */ 58 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ 59 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ 60 61 /* EMAC register related defines */ 62 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) 63 #define EMAC_NUM_MULTICAST_BITS (64) 64 #define EMAC_TEARDOWN_VALUE (0xFFFFFFFC) 65 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) 66 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) 67 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) 68 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) 69 #define EMAC_INT_MASK_CLEAR (0xFF) 70 71 /* RX MBP register bit positions */ 72 #define EMAC_RXMBP_PASSCRC_MASK BIT(30) 73 #define EMAC_RXMBP_QOSEN_MASK BIT(29) 74 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28) 75 #define EMAC_RXMBP_CMFEN_MASK BIT(24) 76 #define EMAC_RXMBP_CSFEN_MASK BIT(23) 77 #define EMAC_RXMBP_CEFEN_MASK BIT(22) 78 #define EMAC_RXMBP_CAFEN_MASK BIT(21) 79 #define EMAC_RXMBP_PROMCH_SHIFT (16) 80 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) 81 #define EMAC_RXMBP_BROADEN_MASK BIT(13) 82 #define EMAC_RXMBP_BROADCH_SHIFT (8) 83 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) 84 #define EMAC_RXMBP_MULTIEN_MASK BIT(5) 85 #define EMAC_RXMBP_MULTICH_SHIFT (0) 86 #define EMAC_RXMBP_MULTICH_MASK (0x7) 87 #define EMAC_RXMBP_CHMASK (0x7) 88 89 /* EMAC register definitions/bit maps used */ 90 # define EMAC_MBP_RXPROMISC (0x00200000) 91 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) 92 # define EMAC_MBP_RXBCAST (0x00002000) 93 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) 94 # define EMAC_MBP_RXMCAST (0x00000020) 95 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) 96 97 /* EMAC mac_control register */ 98 #define EMAC_MACCONTROL_TXPTYPE BIT(9) 99 #define EMAC_MACCONTROL_TXPACEEN BIT(6) 100 #define EMAC_MACCONTROL_GMIIEN BIT(5) 101 #define EMAC_MACCONTROL_GIGABITEN BIT(7) 102 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) 103 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) 104 105 /* GIGABIT MODE related bits */ 106 #define EMAC_DM646X_MACCONTORL_GIG BIT(7) 107 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) 108 109 /* EMAC mac_status register */ 110 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) 111 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) 112 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7) 113 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16) 114 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) 115 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) 116 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7) 117 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8) 118 119 /* EMAC RX register masks */ 120 #define EMAC_RX_MAX_LEN_MASK (0xFFFF) 121 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) 122 123 /* MAC_IN_VECTOR (0x180) register bit fields */ 124 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) 125 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) 126 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) 127 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) 128 129 /** NOTE:: For DM646x the IN_VECTOR has changed */ 130 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) 131 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) 132 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) 133 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) 134 135 /* CPPI bit positions */ 136 #define EMAC_CPPI_SOP_BIT BIT(31) 137 #define EMAC_CPPI_EOP_BIT BIT(30) 138 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29) 139 #define EMAC_CPPI_EOQ_BIT BIT(28) 140 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) 141 #define EMAC_CPPI_PASS_CRC_BIT BIT(26) 142 #define EMAC_RX_BD_BUF_SIZE (0xFFFF) 143 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ 144 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) 145 146 /* Max hardware defines */ 147 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ 148 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ 149 150 /* EMAC Peripheral Device Register Memory Layout structure */ 151 #define EMAC_TXIDVER 0x0 152 #define EMAC_TXCONTROL 0x4 153 #define EMAC_TXTEARDOWN 0x8 154 #define EMAC_RXIDVER 0x10 155 #define EMAC_RXCONTROL 0x14 156 #define EMAC_RXTEARDOWN 0x18 157 #define EMAC_TXINTSTATRAW 0x80 158 #define EMAC_TXINTSTATMASKED 0x84 159 #define EMAC_TXINTMASKSET 0x88 160 #define EMAC_TXINTMASKCLEAR 0x8C 161 #define EMAC_MACINVECTOR 0x90 162 163 #define EMAC_DM646X_MACEOIVECTOR 0x94 164 165 #define EMAC_RXINTSTATRAW 0xA0 166 #define EMAC_RXINTSTATMASKED 0xA4 167 #define EMAC_RXINTMASKSET 0xA8 168 #define EMAC_RXINTMASKCLEAR 0xAC 169 #define EMAC_MACINTSTATRAW 0xB0 170 #define EMAC_MACINTSTATMASKED 0xB4 171 #define EMAC_MACINTMASKSET 0xB8 172 #define EMAC_MACINTMASKCLEAR 0xBC 173 174 #define EMAC_RXMBPENABLE 0x100 175 #define EMAC_RXUNICASTSET 0x104 176 #define EMAC_RXUNICASTCLEAR 0x108 177 #define EMAC_RXMAXLEN 0x10C 178 #define EMAC_RXBUFFEROFFSET 0x110 179 #define EMAC_RXFILTERLOWTHRESH 0x114 180 181 #define EMAC_MACCONTROL 0x160 182 #define EMAC_MACSTATUS 0x164 183 #define EMAC_EMCONTROL 0x168 184 #define EMAC_FIFOCONTROL 0x16C 185 #define EMAC_MACCONFIG 0x170 186 #define EMAC_SOFTRESET 0x174 187 #define EMAC_MACSRCADDRLO 0x1D0 188 #define EMAC_MACSRCADDRHI 0x1D4 189 #define EMAC_MACHASH1 0x1D8 190 #define EMAC_MACHASH2 0x1DC 191 #define EMAC_MACADDRLO 0x500 192 #define EMAC_MACADDRHI 0x504 193 #define EMAC_MACINDEX 0x508 194 195 /* EMAC HDP and Completion registors */ 196 #define EMAC_TXHDP(ch) (0x600 + (ch * 4)) 197 #define EMAC_RXHDP(ch) (0x620 + (ch * 4)) 198 #define EMAC_TXCP(ch) (0x640 + (ch * 4)) 199 #define EMAC_RXCP(ch) (0x660 + (ch * 4)) 200 201 /* EMAC statistics registers */ 202 #define EMAC_RXGOODFRAMES 0x200 203 #define EMAC_RXBCASTFRAMES 0x204 204 #define EMAC_RXMCASTFRAMES 0x208 205 #define EMAC_RXPAUSEFRAMES 0x20C 206 #define EMAC_RXCRCERRORS 0x210 207 #define EMAC_RXALIGNCODEERRORS 0x214 208 #define EMAC_RXOVERSIZED 0x218 209 #define EMAC_RXJABBER 0x21C 210 #define EMAC_RXUNDERSIZED 0x220 211 #define EMAC_RXFRAGMENTS 0x224 212 #define EMAC_RXFILTERED 0x228 213 #define EMAC_RXQOSFILTERED 0x22C 214 #define EMAC_RXOCTETS 0x230 215 #define EMAC_TXGOODFRAMES 0x234 216 #define EMAC_TXBCASTFRAMES 0x238 217 #define EMAC_TXMCASTFRAMES 0x23C 218 #define EMAC_TXPAUSEFRAMES 0x240 219 #define EMAC_TXDEFERRED 0x244 220 #define EMAC_TXCOLLISION 0x248 221 #define EMAC_TXSINGLECOLL 0x24C 222 #define EMAC_TXMULTICOLL 0x250 223 #define EMAC_TXEXCESSIVECOLL 0x254 224 #define EMAC_TXLATECOLL 0x258 225 #define EMAC_TXUNDERRUN 0x25C 226 #define EMAC_TXCARRIERSENSE 0x260 227 #define EMAC_TXOCTETS 0x264 228 #define EMAC_NETOCTETS 0x280 229 #define EMAC_RXSOFOVERRUNS 0x284 230 #define EMAC_RXMOFOVERRUNS 0x288 231 #define EMAC_RXDMAOVERRUNS 0x28C 232 233 /* EMAC DM644x control registers */ 234 #define EMAC_CTRL_EWCTL (0x4) 235 #define EMAC_CTRL_EWINTTCNT (0x8) 236 237 /* EMAC MDIO related */ 238 /* Mask & Control defines */ 239 #define MDIO_CONTROL_CLKDIV (0xFF) 240 #define MDIO_CONTROL_ENABLE BIT(30) 241 #define MDIO_USERACCESS_GO BIT(31) 242 #define MDIO_USERACCESS_WRITE BIT(30) 243 #define MDIO_USERACCESS_READ (0) 244 #define MDIO_USERACCESS_REGADR (0x1F << 21) 245 #define MDIO_USERACCESS_PHYADR (0x1F << 16) 246 #define MDIO_USERACCESS_DATA (0xFFFF) 247 #define MDIO_USERPHYSEL_LINKSEL BIT(7) 248 #define MDIO_VER_MODID (0xFFFF << 16) 249 #define MDIO_VER_REVMAJ (0xFF << 8) 250 #define MDIO_VER_REVMIN (0xFF) 251 252 #define MDIO_USERACCESS(inst) (0x80 + (inst * 8)) 253 #define MDIO_USERPHYSEL(inst) (0x84 + (inst * 8)) 254 #define MDIO_CONTROL (0x04) 255 256 /* EMAC DM646X control module registers */ 257 #define EMAC_DM646X_CMRXINTEN (0x14) 258 #define EMAC_DM646X_CMTXINTEN (0x18) 259 260 /* EMAC EOI codes for C0 */ 261 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) 262 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) 263 264 /* EMAC Stats Clear Mask */ 265 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) 266 267 /** net_buf_obj: EMAC network bufferdata structure 268 * 269 * EMAC network buffer data structure 270 */ 271 struct emac_netbufobj { 272 void *buf_token; 273 char *data_ptr; 274 int length; 275 }; 276 277 /** net_pkt_obj: EMAC network packet data structure 278 * 279 * EMAC network packet data structure - supports buffer list (for future) 280 */ 281 struct emac_netpktobj { 282 void *pkt_token; /* data token may hold tx/rx chan id */ 283 struct emac_netbufobj *buf_list; /* array of network buffer objects */ 284 int num_bufs; 285 int pkt_length; 286 }; 287 288 /** emac_tx_bd: EMAC TX Buffer descriptor data structure 289 * 290 * EMAC TX Buffer descriptor data structure 291 */ 292 struct emac_tx_bd { 293 int h_next; 294 int buff_ptr; 295 int off_b_len; 296 int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */ 297 struct emac_tx_bd __iomem *next; 298 void *buf_token; 299 }; 300 301 /** emac_txch: EMAC TX Channel data structure 302 * 303 * EMAC TX Channel data structure 304 */ 305 struct emac_txch { 306 /* Config related */ 307 rt_uint32_t num_bd; 308 rt_uint32_t service_max; 309 310 /* CPPI specific */ 311 rt_uint32_t alloc_size; 312 void __iomem *bd_mem; 313 struct emac_tx_bd __iomem *bd_pool_head; 314 struct emac_tx_bd __iomem *active_queue_head; 315 struct emac_tx_bd __iomem *active_queue_tail; 316 struct emac_tx_bd __iomem *last_hw_bdprocessed; 317 rt_uint32_t queue_active; 318 rt_uint32_t teardown_pending; 319 rt_uint32_t *tx_complete; 320 321 /** statistics */ 322 rt_uint32_t proc_count; /* TX: # of times emac_tx_bdproc is called */ 323 rt_uint32_t mis_queued_packets; 324 rt_uint32_t queue_reinit; 325 rt_uint32_t end_of_queue_add; 326 rt_uint32_t out_of_tx_bd; 327 rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */ 328 rt_uint32_t active_queue_count; 329 }; 330 331 /** emac_rx_bd: EMAC RX Buffer descriptor data structure 332 * 333 * EMAC RX Buffer descriptor data structure 334 */ 335 struct emac_rx_bd { 336 int h_next; 337 int buff_ptr; 338 int off_b_len; 339 int mode; 340 struct emac_rx_bd __iomem *next; 341 void *data_ptr; 342 void *buf_token; 343 }; 344 345 /** emac_rxch: EMAC RX Channel data structure 346 * 347 * EMAC RX Channel data structure 348 */ 349 struct emac_rxch { 350 /* configuration info */ 351 rt_uint32_t num_bd; 352 rt_uint32_t service_max; 353 rt_uint32_t buf_size; 354 char mac_addr[6]; 355 356 /** CPPI specific */ 357 rt_uint32_t alloc_size; 358 void __iomem *bd_mem; 359 struct emac_rx_bd __iomem *bd_pool_head; 360 struct emac_rx_bd __iomem *active_queue_head; 361 struct emac_rx_bd __iomem *active_queue_tail; 362 rt_uint32_t queue_active; 363 rt_uint32_t teardown_pending; 364 365 /* packet and buffer objects */ 366 struct emac_netpktobj pkt_queue; 367 struct emac_netbufobj buf_queue; 368 369 /** statistics */ 370 rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */ 371 rt_uint32_t processed_bd; 372 rt_uint32_t recycled_bd; 373 rt_uint32_t out_of_rx_bd; 374 rt_uint32_t out_of_rx_buffers; 375 rt_uint32_t queue_reinit; 376 rt_uint32_t end_of_queue_add; 377 rt_uint32_t end_of_queue; 378 rt_uint32_t mis_queued_packets; 379 }; 380 381 struct net_device_stats 382 { 383 unsigned long rx_packets; /* total packets received */ 384 unsigned long tx_packets; /* total packets transmitted */ 385 unsigned long rx_bytes; /* total bytes received */ 386 unsigned long tx_bytes; /* total bytes transmitted */ 387 unsigned long rx_errors; /* bad packets received */ 388 unsigned long tx_errors; /* packet transmit problems */ 389 unsigned long rx_dropped; /* no space in linux buffers */ 390 unsigned long tx_dropped; /* no space available in linux */ 391 unsigned long multicast; /* multicast packets received */ 392 unsigned long collisions; 393 394 /* detailed rx_errors: */ 395 unsigned long rx_length_errors; 396 unsigned long rx_over_errors; /* receiver ring buff overflow */ 397 unsigned long rx_crc_errors; /* recved pkt with crc error */ 398 unsigned long rx_frame_errors; /* recv'd frame alignment error */ 399 unsigned long rx_fifo_errors; /* recv'r fifo overrun */ 400 unsigned long rx_missed_errors; /* receiver missed packet */ 401 402 /* detailed tx_errors */ 403 unsigned long tx_aborted_errors; 404 unsigned long tx_carrier_errors; 405 unsigned long tx_fifo_errors; 406 unsigned long tx_heartbeat_errors; 407 unsigned long tx_window_errors; 408 409 /* for cslip etc */ 410 unsigned long rx_compressed; 411 unsigned long tx_compressed; 412 }; 413 414 415 /* emac_priv: EMAC private data structure 416 * 417 * EMAC adapter private data structure 418 */ 419 #define MAX_ADDR_LEN 6 420 421 struct emac_priv { 422 /* inherit from ethernet device */ 423 struct eth_device parent; 424 425 /* interface address info. */ 426 rt_uint8_t mac_addr[MAX_ADDR_LEN]; /* hw address */ 427 unsigned short phy_addr; 428 429 struct rt_semaphore tx_lock; 430 struct rt_semaphore rx_lock; 431 void __iomem *remap_addr; 432 rt_uint32_t emac_base_phys; 433 void __iomem *emac_base; 434 void __iomem *ctrl_base; 435 void __iomem *emac_ctrl_ram; 436 void __iomem *mdio_base; 437 rt_uint32_t ctrl_ram_size; 438 rt_uint32_t hw_ram_addr; 439 struct emac_txch *txch[EMAC_DEF_MAX_TX_CH]; 440 struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH]; 441 rt_uint32_t link; /* 1=link on, 0=link off */ 442 rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ 443 rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */ 444 rt_uint32_t rx_buf_size; 445 rt_uint32_t isr_count; 446 rt_uint8_t rmii_en; 447 rt_uint8_t version; 448 struct net_device_stats net_dev_stats; 449 rt_uint32_t mac_hash1; 450 rt_uint32_t mac_hash2; 451 rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; 452 rt_uint32_t rx_addr_type; 453 /* periodic timer required for MDIO polling */ 454 struct rt_timer timer; 455 rt_uint32_t periodic_ticks; 456 rt_uint32_t timer_active; 457 rt_uint32_t phy_mask; 458 /* mii_bus,phy members */ 459 struct rt_semaphore lock; 460 }; 461 462 463 #endif /* _DAVINCI_EMAC_H */ 464 465