1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file HAL_eth.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE HAL_eth.h EXAMPLES. 5 /// //////////////////////////////////////////////////////////////////////////// 6 /// @attention 7 /// 8 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 9 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 10 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 11 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 12 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 13 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 14 /// 15 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 16 //////////////////////////////////////////////////////////////////////////////// 17 18 #ifndef __HAL_ETH_H 19 #define __HAL_ETH_H 20 21 // Files includes 22 #include "types.h" 23 #include "mm32_device.h" 24 #include "hal_eth_conf.h" 25 //////////////////////////////////////////////////////////////////////////////// 26 /// @addtogroup MM32_Hardware_Abstract_Layer 27 /// @{ 28 29 //////////////////////////////////////////////////////////////////////////////// 30 /// @defgroup ETH_HAL 31 /// @brief ETH HAL modules 32 /// @{ 33 34 //////////////////////////////////////////////////////////////////////////////// 35 /// @defgroup ETH_Exported_Types 36 /// @{ 37 38 39 //////////////////////////////////////////////////////////////////////////////// 40 41 //////////////////////////////////////////////////////////////////////////////// 42 // ETH | Header | Extra | VLAN tag | Payload | CRC | 43 // Size | 14 | 2 | 4 | 46 ~ 1500 | 4 | 44 #define ETH_MAX_PACKET_SIZE 1524 45 #define ETH_HEADER 14 ///< MAC Dest Addr 6 byte + MAC Src Addr 6 byte + Lenth/Type 2 byte 46 #define ETH_EXTRA 2 47 #define VLAN_TAG 4 48 #define ETH_PAYLOAD_MIN 46 49 #define ETH_PAYLOAD_MAX 1500 50 #define JUMBO_FRAME_PAYLOAD 9000 51 52 #ifndef ETH_RX_BUF_SIZE 53 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 54 #endif 55 56 #ifndef ETH_RX_BUF_NUM 57 #define ETH_RX_BUF_NUM 4 58 #endif 59 60 #ifndef ETH_TX_BUF_SIZE 61 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 62 #endif 63 64 #ifndef ETH_TX_BUF_NUM 65 #define ETH_TX_BUF_NUM 4 66 #endif 67 68 #define ETH_DMA_RDES_FL_Pos 16 ///< Ethernet DMA Received Frame Length Position 69 70 #define ETH_WAKEUP_REGISTER_LENGTH 8 ///< ETHERNET Remote Wake-up frame register length 71 72 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 ///< ETHERNET Missed frames counter Shift 73 74 #define ETH_DMA_TDES_COLLISION_COUNTSHIFT 3 ///< ETHERNET DMA Tx descriptors Collision Count Shift 75 #define ETH_DMA_TDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Tx descriptors Buffer2 Size Shift 76 77 #define ETH_DMA_RDES_FRAME_LENGTHSHIFT 16 ///< ETHERNET DMA Rx descriptors Frame Length Shift 78 #define ETH_DMA_RDES_BUFFER2_SIZESHIFT 11 ///< ETHERNET DMA Rx descriptors Buffer2 Size Shift 79 80 ///< ETHERNET errors 81 #define ETH_ERROR ((u32)0) 82 #define ETH_SUCCESS ((u32)1) 83 84 85 #ifdef _HAL_ETH_C_ 86 #define GLOBAL 87 88 #else 89 #define GLOBAL extern 90 #endif 91 92 93 //////////////////////////////////////////////////////////////////////////////// 94 /// @brief ETH Init Structure Definition 95 //////////////////////////////////////////////////////////////////////////////// 96 typedef struct { 97 __IO u32 ETH_AutoNegotiation; 98 __IO u32 ETH_Watchdog; 99 __IO u32 ETH_Jabber; 100 __IO u32 ETH_InterFrameGap; 101 __IO u32 ETH_CarrierSense; 102 __IO u32 ETH_Speed; 103 __IO u32 ETH_ReceiveOwn; 104 __IO u32 ETH_LoopbackMode; 105 __IO u32 ETH_Mode; 106 __IO u32 ETH_ChecksumOffload; 107 __IO u32 ETH_RetryTransmission; 108 __IO u32 ETH_AutomaticPadCRCStrip; 109 __IO u32 ETH_BackOffLimit; 110 __IO u32 ETH_DeferralCheck; 111 __IO u32 ETH_ReceiveAll; 112 __IO u32 ETH_SourceAddrFilter; 113 __IO u32 ETH_PassControlFrames; 114 __IO u32 ETH_BroadcastFramesReception; 115 __IO u32 ETH_DestinationAddrFilter; 116 __IO u32 ETH_PromiscuousMode; 117 __IO u32 ETH_MulticastFramesFilter; 118 __IO u32 ETH_UnicastFramesFilter; 119 __IO u32 ETH_HashTableHigh; 120 __IO u32 ETH_HashTableLow; 121 __IO u32 ETH_PauseTime; 122 __IO u32 ETH_ZeroQuantaPause; 123 __IO u32 ETH_PauseLowThreshold; 124 __IO u32 ETH_UnicastPauseFrameDetect; 125 __IO u32 ETH_ReceiveFlowControl; 126 __IO u32 ETH_TransmitFlowControl; 127 __IO u32 ETH_VLANTagComparison; 128 __IO u32 ETH_VLANTagIdentifier; 129 __IO u32 ETH_DropTCPIPChecksumErrorFrame; 130 __IO u32 ETH_ReceiveStoreForward; 131 __IO u32 ETH_FlushReceivedFrame; 132 __IO u32 ETH_TransmitStoreForward; 133 __IO u32 ETH_TransmitThresholdControl; 134 __IO u32 ETH_ForwardErrorFrames; 135 __IO u32 ETH_ForwardUndersizedGoodFrames; 136 __IO u32 ETH_ReceiveThresholdControl; 137 __IO u32 ETH_SecondFrameOperate; 138 __IO u32 ETH_AddressAlignedBeats; 139 __IO u32 ETH_FixedBurst; 140 __IO u32 ETH_RxDMABurstLength; 141 __IO u32 ETH_TxDMABurstLength; 142 __IO u32 ETH_DescriptorSkipLength; 143 __IO u32 ETH_DMAArbitration; 144 } ETH_InitTypeDef; 145 146 typedef struct { 147 __IO u32 CS; ///< Control and Status 148 __IO u32 BL; ///< Buffer1, Buffer2 lengths 149 __IO u32 BUF1ADDR; ///< Buffer1 address pointer 150 __IO u32 BUF2NDADDR; ///< Buffer2 or next descriptor address pointer 151 152 #ifdef USE_ENHANCED_DMA_DESCRIPTORS ///< Enhanced ETHERNET DMA PTP Descriptors 153 __IO u32 ExtendedStatus; ///< Extended status for PTP receive descriptor 154 __IO u32 Reserved1; ///< Reserved 155 __IO u32 TimeStampLow; ///< Time Stamp Low value for transmit and receive 156 __IO u32 TimeStampHigh; ///< Time Stamp High value for transmit and receive 157 #endif 158 } ETH_DMADESCTypeDef; 159 160 typedef struct { 161 __IO u32 len; 162 __IO u32 buf; 163 __IO ETH_DMADESCTypeDef* ptrDesc; 164 } FrameTypeDef; 165 166 typedef struct { 167 __IO ETH_DMADESCTypeDef* ptrFS_Rx_Desc; ///< First Segment Rx Desc 168 __IO ETH_DMADESCTypeDef* ptrLS_Rx_Desc; ///< Last Segment Rx Desc 169 __IO u32 cnt; ///< Segment count 170 } ETH_DMA_Rx_Frame_infos; 171 172 173 174 #define ETH_DMA_TDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine 175 #define ETH_DMA_TDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT 176 #define ETH_DMA_TDES_JT ((u32)0x00004000) ///< Jabber Timeout 177 #define ETH_DMA_TDES_FF ((u32)0x00002000) ///< Frame Flushed: DMA/MTL flushed the frame due to SW flush 178 #define ETH_DMA_TDES_LCA ((u32)0x00000800) ///< Loss of Carrier: carrier lost during transmission 179 #define ETH_DMA_TDES_NC ((u32)0x00000400) ///< No Carrier: no carrier signal from the transceiver 180 #define ETH_DMA_TDES_LCO ((u32)0x00000200) ///< Late Collision: transmission aborted due to collision 181 #define ETH_DMA_TDES_EC ((u32)0x00000100) ///< Excessive Collision: transmission aborted after 16 collisions 182 #define ETH_DMA_TDES_VF ((u32)0x00000080) ///< VLAN Frame 183 #define ETH_DMA_TDES_CC ((u32)0x00000078) ///< Collision Count 184 #define ETH_DMA_TDES_ED ((u32)0x00000004) ///< Excessive Deferral 185 #define ETH_DMA_TDES_UF ((u32)0x00000002) ///< Underflow Error: late data arrival from the memory 186 #define ETH_DMA_TDES_DB ((u32)0x00000001) ///< Deferred Bit 187 188 #define ETH_DMA_TDES_IC ((u32)0x80000000) ///< Interrupt on Completion 189 #define ETH_DMA_TDES_LS ((u32)0x40000000) ///< Last Segment 190 #define ETH_DMA_TDES_FS ((u32)0x20000000) ///< First Segment 191 #define ETH_DMA_TDES_DC ((u32)0x04000000) ///< Disable CRC 192 #define ETH_DMA_TDES_TER ((u32)0x02000000) ///< Transmit end of ring 193 #define ETH_DMA_TDES_TCH ((u32)0x01000000) ///< Second Address Chained 194 #define ETH_DMA_TDES_DP ((u32)0x00800000) ///< Disable Padding 195 #define ETH_DMA_TDES_TBS2 ((u32)0x003FF800) ///< Transmit Buffer 2 Size 196 #define ETH_DMA_TDES_TBS1 ((u32)0x000007FF) ///< Transmit Buffer 1 Size 197 198 #define ETH_DMA_TDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer 199 200 #define ETH_DMA_TDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer 201 202 #if defined(USE_ENHANCED_DMA_DESCRIPTORS) 203 #define ETH_DMA_PTP_TDES_TTSL ((u32)0xFFFFFFFF) ///< Transmit Time Stamp Low 204 #define ETH_DMA_PTP_TDES_TTSH ((u32)0xFFFFFFFF) ///< Transmit Time Stamp High 205 #endif 206 207 #define ETH_DMA_RDES_OWN ((u32)0x80000000) ///< OWN bit: descriptor is owned by DMA engine 208 #define ETH_DMA_RDES_AFM ((u32)0x40000000) ///< DA Filter Fail for the rx frame 209 #define ETH_DMA_RDES_FL ((u32)0x3FFF0000) ///< Receive descriptor frame length 210 #define ETH_DMA_RDES_ES ((u32)0x00008000) ///< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE 211 #define ETH_DMA_RDES_DE ((u32)0x00004000) ///< Descriptor error: no more descriptors for receive frame 212 #define ETH_DMA_RDES_SAF ((u32)0x00002000) ///< SA Filter Fail for the received frame 213 #define ETH_DMA_RDES_LE ((u32)0x00001000) ///< Frame size not matching with length field 214 #define ETH_DMA_RDES_OE ((u32)0x00000800) ///< Overflow Error: Frame was damaged due to buffer overflow 215 #define ETH_DMA_RDES_VLAN ((u32)0x00000400) ///< VLAN Tag: received frame is a VLAN frame 216 #define ETH_DMA_RDES_FS ((u32)0x00000200) ///< First descriptor of the frame 217 #define ETH_DMA_RDES_LS ((u32)0x00000100) ///< Last descriptor of the frame 218 #define ETH_DMA_RDES_IPV4HCE ((u32)0x00000080) ///< IPC Checksum Error: Rx Ipv4 header checksum error 219 #define ETH_DMA_RDES_LC ((u32)0x00000040) ///< Late collision occurred during reception 220 #define ETH_DMA_RDES_FT ((u32)0x00000020) ///< Frame type - Ethernet, otherwise 802.3 221 #define ETH_DMA_RDES_RWT ((u32)0x00000010) ///< Receive Watchdog Timeout: watchdog timer expired during reception 222 #define ETH_DMA_RDES_RE ((u32)0x00000008) ///< Receive error: error reported by MII interface 223 #define ETH_DMA_RDES_DBE ((u32)0x00000004) ///< Dribble bit error: frame contains non int multiple of 8 bits 224 #define ETH_DMA_RDES_CE ((u32)0x00000002) ///< CRC error 225 #define ETH_DMA_RDES_MAMPCE ((u32)0x00000001) ///< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error 226 227 #define ETH_DMA_RDES_DIC ((u32)0x80000000) ///< Disable Interrupt on Completion 228 #define ETH_DMA_RDES_RER ((u32)0x02000000) ///< Receive End of Ring 229 #define ETH_DMA_RDES_RCH ((u32)0x01000000) ///< Second Address Chained 230 #define ETH_DMA_RDES_RBS2 ((u32)0x003FF800) ///< Receive Buffer2 Size 231 #define ETH_DMA_RDES_RBS1 ((u32)0x000007FF) ///< Receive Buffer1 Size 232 233 #define ETH_DMA_RDES_B1AP ((u32)0xFFFFFFFF) ///< Buffer 1 Address Pointer 234 235 #define ETH_DMA_RDES_B2AP ((u32)0xFFFFFFFF) ///< Buffer 2 Address Pointer 236 237 238 #if defined(USE_ENHANCED_DMA_DESCRIPTORS) 239 #define ETH_DMA_PTP_RDES_PTPV ((u32)0x00002000) ///< PTP Version 240 #define ETH_DMA_PTP_RDES_PTPFT ((u32)0x00001000) ///< PTP Frame Type 241 #define ETH_DMA_PTP_RDES_PTPMT ((u32)0x00000F00) ///< PTP Message Type 242 #define ETH_DMA_PTP_RDES_PTPMT_Sync ((u32)0x00000100) ///< SYNC message (all clock types) 243 #define ETH_DMA_PTP_RDES_PTPMT_FollowUp ((u32)0x00000200) ///< FollowUp message (all clock types) 244 #define ETH_DMA_PTP_RDES_PTPMT_DelayReq ((u32)0x00000300) ///< DelayReq message (all clock types) 245 #define ETH_DMA_PTP_RDES_PTPMT_DelayResp ((u32)0x00000400) ///< DelayResp message (all clock types) 246 #define ETH_DMA_PTP_RDES_PTPMT_PdelayReq_Announce ((u32)0x00000500) ///< PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) 247 #define ETH_DMA_PTP_RDES_PTPMT_PdelayResp_Manag ((u32)0x00000600) ///< PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) 248 #define ETH_DMA_PTP_RDES_PTPMT_PdelayRespFollowUp_Signal ((u32)0x00000700) ///< PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) 249 #define ETH_DMA_PTP_RDES_IPV6PR ((u32)0x00000080) ///< IPv6 Packet Received 250 #define ETH_DMA_PTP_RDES_IPV4PR ((u32)0x00000040) ///< IPv4 Packet Received 251 #define ETH_DMA_PTP_RDES_IPCB ((u32)0x00000020) ///< IP Checksum Bypassed 252 #define ETH_DMA_PTP_RDES_IPPE ((u32)0x00000010) ///< IP Payload Error 253 #define ETH_DMA_PTP_RDES_IPHE ((u32)0x00000008) ///< IP Header Error 254 #define ETH_DMA_PTP_RDES_IPPT ((u32)0x00000007) ///< IP Payload Type 255 #define ETH_DMA_PTP_RDES_IPPT_UDP ((u32)0x00000001) ///< UDP payload encapsulated in the IP datagram 256 #define ETH_DMA_PTP_RDES_IPPT_TCP ((u32)0x00000002) ///< TCP payload encapsulated in the IP datagram 257 #define ETH_DMA_PTP_RDES_IPPT_ICMP ((u32)0x00000003) ///< ICMP payload encapsulated in the IP datagram 258 259 260 261 #define ETH_DMA_PTP_RDES_TTSL ((u32)0xFFFFFFFF) ///< Receive Time Stamp Low 262 #define ETH_DMA_PTP_RDES_TTSH ((u32)0xFFFFFFFF) ///< Receive Time Stamp High 263 #endif 264 265 //////////////////////////////////////////////////////////////////////////////// 266 #define PHY_READ_TIMEOUT ((u32)0x0004FFFF) 267 #define PHY_WRITE_TIMEOUT ((u32)0x0004FFFF) 268 269 #define PHY_BCR 0 ///< Transceiver Basic Control Register 270 #define PHY_BSR 1 ///< Transceiver Basic Status Register 271 272 #define PHY_Reset ((u16)0x8000) ///< PHY Reset 273 #define PHY_Loopback ((u16)0x4000) ///< Select loop-back mode 274 #define PHY_FULLDUPLEX_100M ((u16)0x2100) ///< Set the full-duplex mode at 100 Mb/s 275 #define PHY_HALFDUPLEX_100M ((u16)0x2000) ///< Set the half-duplex mode at 100 Mb/s 276 #define PHY_FULLDUPLEX_10M ((u16)0x0100) ///< Set the full-duplex mode at 10 Mb/s 277 #define PHY_HALFDUPLEX_10M ((u16)0x0000) ///< Set the half-duplex mode at 10 Mb/s 278 #define PHY_AutoNegotiation ((u16)0x1000) ///< Enable auto-negotiation function 279 #define PHY_Restart_AutoNegotiation ((u16)0x0200) ///< Restart auto-negotiation function 280 #define PHY_Powerdown ((u16)0x0800) ///< Select the power down mode 281 #define PHY_Isolate ((u16)0x0400) ///< Isolate PHY from MII 282 283 #define PHY_AutoNego_Complete ((u16)0x0020) ///< Auto-Negotiation process completed 284 #define PHY_Linked_Status ((u16)0x0004) ///< Valid link established 285 #define PHY_Jabber_detection ((u16)0x0002) ///< Jabber condition detected 286 287 //////////////////////////////////////////////////////////////////////////////// 288 #define ETH_AutoNegotiation_Enable ((u32)0x00000001) 289 #define ETH_AutoNegotiation_Disable ((u32)0x00000000) 290 291 #define ETH_Watchdog_Enable ((u32)0x00000000) 292 #define ETH_Watchdog_Disable ((u32)0x00800000) 293 294 #define ETH_Jabber_Enable ((u32)0x00000000) 295 #define ETH_Jabber_Disable ((u32)0x00400000) 296 297 #define ETH_InterFrameGap_96Bit ((u32)0x00000000) ///< minimum IFG between frames during transmission is 96Bit 298 #define ETH_InterFrameGap_88Bit ((u32)0x00020000) ///< minimum IFG between frames during transmission is 88Bit 299 #define ETH_InterFrameGap_80Bit ((u32)0x00040000) ///< minimum IFG between frames during transmission is 80Bit 300 #define ETH_InterFrameGap_72Bit ((u32)0x00060000) ///< minimum IFG between frames during transmission is 72Bit 301 #define ETH_InterFrameGap_64Bit ((u32)0x00080000) ///< minimum IFG between frames during transmission is 64Bit 302 #define ETH_InterFrameGap_56Bit ((u32)0x000A0000) ///< minimum IFG between frames during transmission is 56Bit 303 #define ETH_InterFrameGap_48Bit ((u32)0x000C0000) ///< minimum IFG between frames during transmission is 48Bit 304 #define ETH_InterFrameGap_40Bit ((u32)0x000E0000) ///< minimum IFG between frames during transmission is 40Bit 305 306 #define ETH_CarrierSense_Enable ((u32)0x00000000) 307 #define ETH_CarrierSense_Disable ((u32)0x00010000) 308 309 #define ETH_Speed_10M ((u32)0x00000000) 310 #define ETH_Speed_100M ((u32)0x00004000) 311 312 #define ETH_ReceiveOwn_Enable ((u32)0x00000000) 313 #define ETH_ReceiveOwn_Disable ((u32)0x00002000) 314 315 #define ETH_LoopbackMode_Enable ((u32)0x00001000) 316 #define ETH_LoopbackMode_Disable ((u32)0x00000000) 317 318 #define ETH_Mode_FullDuplex ((u32)0x00000800) 319 #define ETH_Mode_HalfDuplex ((u32)0x00000000) 320 321 #define ETH_ChecksumOffload_Enable ((u32)0x00000400) 322 #define ETH_ChecksumOffload_Disable ((u32)0x00000000) 323 324 #define ETH_RetryTransmission_Enable ((u32)0x00000000) 325 #define ETH_RetryTransmission_Disable ((u32)0x00000200) 326 327 #define ETH_AutomaticPadCRCStrip_Enable ((u32)0x00000080) 328 #define ETH_AutomaticPadCRCStrip_Disable ((u32)0x00000000) 329 330 #define ETH_BackOffLimit_10 ((u32)0x00000000) 331 #define ETH_BackOffLimit_8 ((u32)0x00000020) 332 #define ETH_BackOffLimit_4 ((u32)0x00000040) 333 #define ETH_BackOffLimit_1 ((u32)0x00000060) 334 335 #define ETH_DeferralCheck_Enable ((u32)0x00000010) 336 #define ETH_DeferralCheck_Disable ((u32)0x00000000) 337 338 #define ETH_ReceiveAll_Enable ((u32)0x80000000) 339 #define ETH_ReceiveAll_Disable ((u32)0x00000000) 340 341 #define ETH_SourceAddrFilter_Normal_Enable ((u32)0x00000200) 342 #define ETH_SourceAddrFilter_Inverse_Enable ((u32)0x00000300) 343 #define ETH_SourceAddrFilter_Disable ((u32)0x00000000) 344 345 #define ETH_PassControlFrames_BlockAll ((u32)0x00000040) ///< MAC filters all control frames from reaching the application 346 #define ETH_PassControlFrames_ForwardAll ((u32)0x00000080) ///< MAC forwards all control frames to application even if they fail the Address Filter 347 #define ETH_PassControlFrames_ForwardPassedAddrFilter ((u32)0x000000C0) ///< MAC forwards control frames that pass the Address Filter. 348 349 #define ETH_BroadcastFramesReception_Enable ((u32)0x00000000) 350 #define ETH_BroadcastFramesReception_Disable ((u32)0x00000020) 351 352 #define ETH_DestinationAddrFilter_Normal ((u32)0x00000000) 353 #define ETH_DestinationAddrFilter_Inverse ((u32)0x00000008) 354 355 #define ETH_PromiscuousMode_Enable ((u32)0x00000001) 356 #define ETH_PromiscuousMode_Disable ((u32)0x00000000) 357 358 #define ETH_MulticastFramesFilter_PerfectHashTable ((u32)0x00000404) 359 #define ETH_MulticastFramesFilter_HashTable ((u32)0x00000004) 360 #define ETH_MulticastFramesFilter_Perfect ((u32)0x00000000) 361 #define ETH_MulticastFramesFilter_None ((u32)0x00000010) 362 363 #define ETH_UnicastFramesFilter_PerfectHashTable ((u32)0x00000402) 364 #define ETH_UnicastFramesFilter_HashTable ((u32)0x00000002) 365 #define ETH_UnicastFramesFilter_Perfect ((u32)0x00000000) 366 367 #define ETH_ZeroQuantaPause_Enable ((u32)0x00000000) 368 #define ETH_ZeroQuantaPause_Disable ((u32)0x00000080) 369 370 #define ETH_PauseLowThreshold_Minus4 ((u32)0x00000000) ///< Pause time minus 4 slot times 371 #define ETH_PauseLowThreshold_Minus28 ((u32)0x00000010) ///< Pause time minus 28 slot times 372 #define ETH_PauseLowThreshold_Minus144 ((u32)0x00000020) ///< Pause time minus 144 slot times 373 #define ETH_PauseLowThreshold_Minus256 ((u32)0x00000030) ///< Pause time minus 256 slot times 374 375 #define ETH_UnicastPauseFrameDetect_Enable ((u32)0x00000008) 376 #define ETH_UnicastPauseFrameDetect_Disable ((u32)0x00000000) 377 378 #define ETH_ReceiveFlowControl_Enable ((u32)0x00000004) 379 #define ETH_ReceiveFlowControl_Disable ((u32)0x00000000) 380 381 #define ETH_TransmitFlowControl_Enable ((u32)0x00000002) 382 #define ETH_TransmitFlowControl_Disable ((u32)0x00000000) 383 384 #define ETH_VLANTagComparison_12Bit ((u32)0x00010000) 385 #define ETH_VLANTagComparison_16Bit ((u32)0x00000000) 386 387 #define ETH_MAC_FLAG_TST ((u32)0x00000200) ///< Time stamp trigger flag (on MAC) 388 #define ETH_MAC_FLAG_MMCT ((u32)0x00000040) ///< MMC transmit flag 389 #define ETH_MAC_FLAG_MMCR ((u32)0x00000020) ///< MMC receive flag 390 #define ETH_MAC_FLAG_MMC ((u32)0x00000010) ///< MMC flag (on MAC) 391 #define ETH_MAC_FLAG_PMT ((u32)0x00000008) ///< PMT flag (on MAC) 392 393 #define ETH_MAC_IT_TST ((u32)0x00000200) ///< Time stamp trigger interrupt (on MAC) 394 #define ETH_MAC_IT_MMCT ((u32)0x00000040) ///< MMC transmit interrupt 395 #define ETH_MAC_IT_MMCR ((u32)0x00000020) ///< MMC receive interrupt 396 #define ETH_MAC_IT_MMC ((u32)0x00000010) ///< MMC interrupt (on MAC) 397 #define ETH_MAC_IT_PMT ((u32)0x00000008) ///< PMT interrupt (on MAC) 398 399 #define ETH_MAC_Address0 ((u32)0x00000000) 400 #define ETH_MAC_Address1 ((u32)0x00000008) 401 #define ETH_MAC_Address2 ((u32)0x00000010) 402 #define ETH_MAC_Address3 ((u32)0x00000018) 403 404 #define ETH_MAC_AddressFilter_SA ((u32)0x00000000) 405 #define ETH_MAC_AddressFilter_DA ((u32)0x00000008) 406 407 #define ETH_MAC_AddressMask_Byte6 ((u32)0x20000000) ///< Mask MAC Address high reg bits [15:8] 408 #define ETH_MAC_AddressMask_Byte5 ((u32)0x10000000) ///< Mask MAC Address high reg bits [7:0] 409 #define ETH_MAC_AddressMask_Byte4 ((u32)0x08000000) ///< Mask MAC Address low reg bits [31:24] 410 #define ETH_MAC_AddressMask_Byte3 ((u32)0x04000000) ///< Mask MAC Address low reg bits [23:16] 411 #define ETH_MAC_AddressMask_Byte2 ((u32)0x02000000) ///< Mask MAC Address low reg bits [15:8] 412 #define ETH_MAC_AddressMask_Byte1 ((u32)0x01000000) ///< Mask MAC Address low reg bits [70] 413 414 //////////////////////////////////////////////////////////////////////////////// 415 #define ETH_DMA_TDES_LastSegment ((u32)0x40000000) ///< Last Segment 416 #define ETH_DMA_TDES_FirstSegment ((u32)0x20000000) ///< First Segment 417 418 #define ETH_DMA_TDES_ChecksumByPass ((u32)0x00000000) ///< Checksum engine bypass 419 #define ETH_DMA_TDES_ChecksumIPV4Header ((u32)0x00400000) ///< IPv4 header checksum insertion 420 #define ETH_DMA_TDES_ChecksumTCPUDPICMPSegment ((u32)0x00800000) ///< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present 421 #define ETH_DMA_TDES_ChecksumTCPUDPICMPFull ((u32)0x00C00000) ///< TCP/UDP/ICMP checksum fully in hardware including pseudo header 422 423 #define ETH_DMA_RDES_Buffer1 ((u32)0x00000000) ///< DMA Rx Desc Buffer1 424 #define ETH_DMA_RDES_Buffer2 ((u32)0x00000001) ///< DMA Rx Desc Buffer2 425 426 #define ETH_DropTCPIPChecksumErrorFrame_Enable ((u32)0x00000000) 427 #define ETH_DropTCPIPChecksumErrorFrame_Disable ((u32)0x04000000) 428 429 #define ETH_ReceiveStoreForward_Enable ((u32)0x02000000) 430 #define ETH_ReceiveStoreForward_Disable ((u32)0x00000000) 431 432 #define ETH_FlushReceivedFrame_Enable ((u32)0x00000000) 433 #define ETH_FlushReceivedFrame_Disable ((u32)0x01000000) 434 435 #define ETH_TransmitStoreForward_Enable ((u32)0x00200000) 436 #define ETH_TransmitStoreForward_Disable ((u32)0x00000000) 437 438 #define ETH_TransmitThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Transmit FIFO is 64 Bytes 439 #define ETH_TransmitThresholdControl_128Bytes ((u32)0x00004000) ///< threshold level of the MTL Transmit FIFO is 128 Bytes 440 #define ETH_TransmitThresholdControl_192Bytes ((u32)0x00008000) ///< threshold level of the MTL Transmit FIFO is 192 Bytes 441 #define ETH_TransmitThresholdControl_256Bytes ((u32)0x0000C000) ///< threshold level of the MTL Transmit FIFO is 256 Bytes 442 #define ETH_TransmitThresholdControl_40Bytes ((u32)0x00010000) ///< threshold level of the MTL Transmit FIFO is 40 Bytes 443 #define ETH_TransmitThresholdControl_32Bytes ((u32)0x00014000) ///< threshold level of the MTL Transmit FIFO is 32 Bytes 444 #define ETH_TransmitThresholdControl_24Bytes ((u32)0x00018000) ///< threshold level of the MTL Transmit FIFO is 24 Bytes 445 #define ETH_TransmitThresholdControl_16Bytes ((u32)0x0001C000) ///< threshold level of the MTL Transmit FIFO is 16 Bytes 446 447 #define ETH_ForwardErrorFrames_Enable ((u32)0x00000080) 448 #define ETH_ForwardErrorFrames_Disable ((u32)0x00000000) 449 450 #define ETH_ForwardUndersizedGoodFrames_Enable ((u32)0x00000040) 451 #define ETH_ForwardUndersizedGoodFrames_Disable ((u32)0x00000000) 452 453 #define ETH_ReceiveThresholdControl_64Bytes ((u32)0x00000000) ///< threshold level of the MTL Receive FIFO is 64 Bytes 454 #define ETH_ReceiveThresholdControl_32Bytes ((u32)0x00000008) ///< threshold level of the MTL Receive FIFO is 32 Bytes 455 #define ETH_ReceiveThresholdControl_96Bytes ((u32)0x00000010) ///< threshold level of the MTL Receive FIFO is 96 Bytes 456 #define ETH_ReceiveThresholdControl_128Bytes ((u32)0x00000018) ///< threshold level of the MTL Receive FIFO is 128 Bytes 457 458 #define ETH_SecondFrameOperate_Enable ((u32)0x00000004) 459 #define ETH_SecondFrameOperate_Disable ((u32)0x00000000) 460 461 #define ETH_AddressAlignedBeats_Enable ((u32)0x02000000) 462 #define ETH_AddressAlignedBeats_Disable ((u32)0x00000000) 463 464 #define ETH_FixedBurst_Enable ((u32)0x00010000) 465 #define ETH_FixedBurst_Disable ((u32)0x00000000) 466 467 #define ETH_RxDMABurstLength_1Beat ((u32)0x00020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 1 468 #define ETH_RxDMABurstLength_2Beat ((u32)0x00040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 2 469 #define ETH_RxDMABurstLength_4Beat ((u32)0x00080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4 470 #define ETH_RxDMABurstLength_8Beat ((u32)0x00100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8 471 #define ETH_RxDMABurstLength_16Beat ((u32)0x00200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16 472 #define ETH_RxDMABurstLength_32Beat ((u32)0x00400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32 473 #define ETH_RxDMABurstLength_4xPBL_4Beat ((u32)0x01020000) ///< maximum number of beats to be transferred in one RxDMA transaction is 4 474 #define ETH_RxDMABurstLength_4xPBL_8Beat ((u32)0x01040000) ///< maximum number of beats to be transferred in one RxDMA transaction is 8 475 #define ETH_RxDMABurstLength_4xPBL_16Beat ((u32)0x01080000) ///< maximum number of beats to be transferred in one RxDMA transaction is 16 476 #define ETH_RxDMABurstLength_4xPBL_32Beat ((u32)0x01100000) ///< maximum number of beats to be transferred in one RxDMA transaction is 32 477 #define ETH_RxDMABurstLength_4xPBL_64Beat ((u32)0x01200000) ///< maximum number of beats to be transferred in one RxDMA transaction is 64 478 #define ETH_RxDMABurstLength_4xPBL_128Beat ((u32)0x01400000) ///< maximum number of beats to be transferred in one RxDMA transaction is 128 479 480 #define ETH_TxDMABurstLength_1Beat ((u32)0x00000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 481 #define ETH_TxDMABurstLength_2Beat ((u32)0x00000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 482 #define ETH_TxDMABurstLength_4Beat ((u32)0x00000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 483 #define ETH_TxDMABurstLength_8Beat ((u32)0x00000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 484 #define ETH_TxDMABurstLength_16Beat ((u32)0x00001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 485 #define ETH_TxDMABurstLength_32Beat ((u32)0x00002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 486 #define ETH_TxDMABurstLength_4xPBL_4Beat ((u32)0x01000100) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 487 #define ETH_TxDMABurstLength_4xPBL_8Beat ((u32)0x01000200) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 488 #define ETH_TxDMABurstLength_4xPBL_16Beat ((u32)0x01000400) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 489 #define ETH_TxDMABurstLength_4xPBL_32Beat ((u32)0x01000800) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 490 #define ETH_TxDMABurstLength_4xPBL_64Beat ((u32)0x01001000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 491 #define ETH_TxDMABurstLength_4xPBL_128Beat ((u32)0x01002000) ///< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 492 493 #define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((u32)0x00000000) 494 #define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((u32)0x00004000) 495 #define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((u32)0x00008000) 496 #define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((u32)0x0000C000) 497 #define ETH_DMAArbitration_RxPriorTx ((u32)0x00000002) 498 499 #define ETH_DMA_FLAG_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA) 500 #define ETH_DMA_FLAG_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA) 501 #define ETH_DMA_FLAG_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA) 502 #define ETH_DMA_FLAG_DataTransferError ((u32)0x00800000) ///< Error bits 0-Rx DMA, 1-Tx DMA 503 #define ETH_DMA_FLAG_ReadWriteError ((u32)0x01000000) ///< Error bits 0-write trnsf, 1-read transfr 504 #define ETH_DMA_FLAG_AccessError ((u32)0x02000000) ///< Error bits 0-data buffer, 1-desc. access 505 #define ETH_DMA_FLAG_NIS ((u32)0x00010000) ///< Normal interrupt summary flag 506 #define ETH_DMA_FLAG_AIS ((u32)0x00008000) ///< Abnormal interrupt summary flag 507 #define ETH_DMA_FLAG_ER ((u32)0x00004000) ///< Early receive flag 508 #define ETH_DMA_FLAG_FBE ((u32)0x00002000) ///< Fatal bus error flag 509 #define ETH_DMA_FLAG_ET ((u32)0x00000400) ///< Early transmit flag 510 #define ETH_DMA_FLAG_RWT ((u32)0x00000200) ///< Receive watchdog timeout flag 511 #define ETH_DMA_FLAG_RPS ((u32)0x00000100) ///< Receive process stopped flag 512 #define ETH_DMA_FLAG_RBU ((u32)0x00000080) ///< Receive buffer unavailable flag 513 #define ETH_DMA_FLAG_R ((u32)0x00000040) ///< Receive flag 514 #define ETH_DMA_FLAG_TU ((u32)0x00000020) ///< Underflow flag 515 #define ETH_DMA_FLAG_RO ((u32)0x00000010) ///< Overflow flag 516 #define ETH_DMA_FLAG_TJT ((u32)0x00000008) ///< Transmit jabber timeout flag 517 #define ETH_DMA_FLAG_TBU ((u32)0x00000004) ///< Transmit buffer unavailable flag 518 #define ETH_DMA_FLAG_TPS ((u32)0x00000002) ///< Transmit process stopped flag 519 #define ETH_DMA_FLAG_T ((u32)0x00000001) ///< Transmit flag 520 521 #define ETH_DMA_IT_TST ((u32)0x20000000) ///< Time-stamp trigger interrupt (on DMA) 522 #define ETH_DMA_IT_PMT ((u32)0x10000000) ///< PMT interrupt (on DMA) 523 #define ETH_DMA_IT_MMC ((u32)0x08000000) ///< MMC interrupt (on DMA) 524 #define ETH_DMA_IT_NIS ((u32)0x00010000) ///< Normal interrupt summary 525 #define ETH_DMA_IT_AIS ((u32)0x00008000) ///< Abnormal interrupt summary 526 #define ETH_DMA_IT_ER ((u32)0x00004000) ///< Early receive interrupt 527 #define ETH_DMA_IT_FBE ((u32)0x00002000) ///< Fatal bus error interrupt 528 #define ETH_DMA_IT_ET ((u32)0x00000400) ///< Early transmit interrupt 529 #define ETH_DMA_IT_RWT ((u32)0x00000200) ///< Receive watchdog timeout interrupt 530 #define ETH_DMA_IT_RPS ((u32)0x00000100) ///< Receive process stopped interrupt 531 #define ETH_DMA_IT_RBU ((u32)0x00000080) ///< Receive buffer unavailable interrupt 532 #define ETH_DMA_IT_R ((u32)0x00000040) ///< Receive interrupt 533 #define ETH_DMA_IT_TU ((u32)0x00000020) ///< Underflow interrupt 534 #define ETH_DMA_IT_RO ((u32)0x00000010) ///< Overflow interrupt 535 #define ETH_DMA_IT_TJT ((u32)0x00000008) ///< Transmit jabber timeout interrupt 536 #define ETH_DMA_IT_TBU ((u32)0x00000004) ///< Transmit buffer unavailable interrupt 537 #define ETH_DMA_IT_TPS ((u32)0x00000002) ///< Transmit process stopped interrupt 538 #define ETH_DMA_IT_T ((u32)0x00000001) ///< Transmit interrupt 539 540 #define ETH_DMA_TransmitProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Tx Command issued 541 #define ETH_DMA_TransmitProcess_Fetching ((u32)0x00100000) ///< Running - fetching the Tx descriptor 542 #define ETH_DMA_TransmitProcess_Waiting ((u32)0x00200000) ///< Running - waiting for status 543 #define ETH_DMA_TransmitProcess_Reading ((u32)0x00300000) ///< Running - reading the data from host memory 544 #define ETH_DMA_TransmitProcess_Suspended ((u32)0x00600000) ///< Suspended - Tx Descriptor unavailable 545 #define ETH_DMA_TransmitProcess_Closing ((u32)0x00700000) ///< Running - closing Rx descriptor 546 547 #define ETH_DMA_ReceiveProcess_Stopped ((u32)0x00000000) ///< Stopped - Reset or Stop Rx Command issued 548 #define ETH_DMA_ReceiveProcess_Fetching ((u32)0x00020000) ///< Running - fetching the Rx descriptor 549 #define ETH_DMA_ReceiveProcess_Waiting ((u32)0x00060000) ///< Running - waiting for packet 550 #define ETH_DMA_ReceiveProcess_Suspended ((u32)0x00080000) ///< Suspended - Rx Descriptor unavailable 551 #define ETH_DMA_ReceiveProcess_Closing ((u32)0x000A0000) ///< Running - closing descriptor 552 #define ETH_DMA_ReceiveProcess_Queuing ((u32)0x000E0000) ///< Running - queuing the receive frame into host memory 553 554 #define ETH_DMA_Overflow_RxFIFOCounter ((u32)0x10000000) ///< Overflow bit for FIFO overflow counter 555 #define ETH_DMA_Overflow_MissedFrameCounter ((u32)0x00010000) ///< Overflow bit for missed frame counter 556 557 //////////////////////////////////////////////////////////////////////////////// 558 #define ETH_PMT_FLAG_WUFFRPR ((u32)0x80000000) ///< Wake-Up Frame Filter Register Pointer Reset 559 #define ETH_PMT_FLAG_WUFR ((u32)0x00000040) ///< Wake-Up Frame Received 560 #define ETH_PMT_FLAG_MPR ((u32)0x00000020) ///< Magic Packet Received 561 562 //////////////////////////////////////////////////////////////////////////////// 563 #define ETH_MMC_IT_TGF ((u32)0x00200000) ///< When Tx good frame counter reaches half the maximum value 564 #define ETH_MMC_IT_TGFMSC ((u32)0x00008000) ///< When Tx good multi col counter reaches half the maximum value 565 #define ETH_MMC_IT_TGFSC ((u32)0x00004000) ///< When Tx good single col counter reaches half the maximum value 566 567 #define ETH_MMC_IT_RGUF ((u32)0x10020000) ///< When Rx good unicast frames counter reaches half the maximum value 568 #define ETH_MMC_IT_RFAE ((u32)0x10000040) ///< When Rx alignment error counter reaches half the maximum value 569 #define ETH_MMC_IT_RFCE ((u32)0x10000020) ///< When Rx crc error counter reaches half the maximum value 570 571 #define ETH_MMCCR ((u32)0x00000100) ///< MMC CR register 572 #define ETH_MMCRIR ((u32)0x00000104) ///< MMC RIR register 573 #define ETH_MMCTIR ((u32)0x00000108) ///< MMC TIR register 574 #define ETH_MMCRIMR ((u32)0x0000010C) ///< MMC RIMR register 575 #define ETH_MMCTIMR ((u32)0x00000110) ///< MMC TIMR register 576 #define ETH_MMCTGFSCCR ((u32)0x0000014C) ///< MMC TGFSCCR register 577 #define ETH_MMCTGFMSCCR ((u32)0x00000150) ///< MMC TGFMSCCR register 578 #define ETH_MMCTGFCR ((u32)0x00000168) ///< MMC TGFCR register 579 #define ETH_MMCRFCECR ((u32)0x00000194) ///< MMC RFCECR register 580 #define ETH_MMCRFAECR ((u32)0x00000198) ///< MMC RFAECR register 581 #define ETH_MMCRGUFCR ((u32)0x000001C4) ///< MMC RGUFCR register 582 583 //////////////////////////////////////////////////////////////////////////////// 584 #define ETH_PTP_FineUpdate ((u32)0x00000001) ///< Fine Update method 585 #define ETH_PTP_CoarseUpdate ((u32)0x00000000) ///< Coarse Update method 586 587 #define ETH_PTP_FLAG_TSARU ((u32)0x00000020) ///< Addend Register Update 588 #define ETH_PTP_FLAG_TSITE ((u32)0x00000010) ///< Time Stamp Interrupt Trigger 589 #define ETH_PTP_FLAG_TSSTU ((u32)0x00000008) ///< Time Stamp Update 590 #define ETH_PTP_FLAG_TSSTI ((u32)0x00000004) ///< Time Stamp Initialize 591 592 #define ETH_PTP_FLAG_TSTTR ((u32)0x10000002) ///< Time stamp target time reached 593 #define ETH_PTP_FLAG_TSSO ((u32)0x10000001) ///< Time stamp seconds overflow 594 595 #define ETH_PTP_PositiveTime ((u32)0x00000000) ///< Positive time value 596 #define ETH_PTP_NegativeTime ((u32)0x80000000) ///< Negative time value 597 598 #define ETH_PTPTSCR ((u32)0x00000700) ///< PTP TSCR register 599 #define ETH_PTPSSIR ((u32)0x00000704) ///< PTP SSIR register 600 #define ETH_PTPTSHR ((u32)0x00000708) ///< PTP TSHR register 601 #define ETH_PTPTSLR ((u32)0x0000070C) ///< PTP TSLR register 602 #define ETH_PTPTSHUR ((u32)0x00000710) ///< PTP TSHUR register 603 #define ETH_PTPTSLUR ((u32)0x00000714) ///< PTP TSLUR register 604 #define ETH_PTPTSAR ((u32)0x00000718) ///< PTP TSAR register 605 #define ETH_PTPTTHR ((u32)0x0000071C) ///< PTP TTHR register 606 #define ETH_PTPTTLR ((u32)0x00000720) ///< PTP TTLR register 607 608 #define ETH_PTPTSSR ((u32)0x00000728) ///< PTP TSSR register 609 610 #define ETH_PTP_OrdinaryClock ((u32)0x00000000) ///< Ordinary Clock 611 #define ETH_PTP_BoundaryClock ((u32)0x00010000) ///< Boundary Clock 612 #define ETH_PTP_EndToEndTransparentClock ((u32)0x00020000) ///< End To End Transparent Clock 613 #define ETH_PTP_PeerToPeerTransparentClock ((u32)0x00030000) ///< Peer To Peer Transparent Clock 614 615 #define ETH_PTP_SnapshotMasterMessage ((u32)0x00008000) ///< Time stamp snapshot for message relevant to master enable 616 #define ETH_PTP_SnapshotEventMessage ((u32)0x00004000) ///< Time stamp snapshot for event message enable 617 #define ETH_PTP_SnapshotIPV4Frames ((u32)0x00002000) ///< Time stamp snapshot for IPv4 frames enable 618 #define ETH_PTP_SnapshotIPV6Frames ((u32)0x00001000) ///< Time stamp snapshot for IPv6 frames enable 619 #define ETH_PTP_SnapshotPTPOverEthernetFrames ((u32)0x00000800) ///< Time stamp snapshot for PTP over ethernet frames enable 620 #define ETH_PTP_SnapshotAllReceivedFrames ((u32)0x00000100) ///< Time stamp snapshot for all received frames enable 621 622 #define ETH_MAC_ADDR_HBASE (ETH_BASE + 0x40) ///< ETHERNET MAC address high offset 623 #define ETH_MAC_ADDR_LBASE (ETH_BASE + 0x44) ///< ETHERNET MAC address low offset 624 625 #define MACMIIAR_CR_MASK ((u32)0xFFFFFFE3) 626 627 #define MACCR_CLEAR_MASK ((u32)0xFF20810F) 628 #define MACFCR_CLEAR_MASK ((u32)0x0000FF41) 629 #define DMAOMR_CLEAR_MASK ((u32)0xF8DE3F23) 630 631 632 633 GLOBAL __IO ETH_DMADESCTypeDef* DMATxDescToSet; 634 GLOBAL __IO ETH_DMADESCTypeDef* DMARxDescToGet; 635 636 GLOBAL ETH_DMA_Rx_Frame_infos RX_Frame_Descriptor; 637 GLOBAL __IO ETH_DMA_Rx_Frame_infos* DMA_RX_FRAME_infos; 638 GLOBAL __IO u32 Frame_Rx_index; 639 640 #undef GLOBAL 641 642 void ETH_DeInit(void); 643 void ETH_StructInit(ETH_InitTypeDef* ptr); 644 u32 ETH_Init(ETH_InitTypeDef* ptr, u16 phy_addr); 645 void ETH_Start(void); 646 void ETH_Stop(void); 647 void ETH_MACTransmissionCmd(FunctionalState sta); 648 void ETH_MACReceptionCmd(FunctionalState sta); 649 FlagStatus ETH_GetFlowControlBusyStatus(void); 650 void ETH_InitiatePauseControlFrame(void); 651 void ETH_BackPressureActivationCmd(FunctionalState sta); 652 void ETH_MACAddressConfig(u32 reg_addr, u8* mac_addr); 653 void ETH_GetMACAddress(u32 reg_addr, u8* mac_addr); 654 void ETH_MACAddressPerfectFilterCmd(u32 reg_addr, FunctionalState sta); 655 void ETH_MACAddressFilterConfig(u32 reg_addr, u32 sta); 656 void ETH_MACAddressMaskBytesFilterConfig(u32 reg_addr, u32 mask_byte); 657 FrameTypeDef ETH_Get_Received_Frame(void); 658 FrameTypeDef ETH_Get_Received_Frame_interrupt(void); 659 u32 ETH_Prepare_Transmit_Descriptors(u16 len); 660 void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt); 661 u32 ETH_CheckFrameReceived(void); 662 void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef* ptr_desc, u8* buf, u32 cnt); 663 FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag); 664 u32 ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef* ptr_desc); 665 void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc); 666 void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); 667 void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val); 668 void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef* ptr_desc, u32 val); 669 void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); 670 void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); 671 void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); 672 void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef* ptr_desc, u32 buf1_size, u32 buf2_size); 673 FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef* ptr_desc, u32 flag); 674 void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef* ptr_desc); 675 u32 ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef* ptr_desc); 676 void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef* ptr_desc, FunctionalState sta); 677 u32 ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef* ptr_desc, u32 buf); 678 u32 ETH_GetRxPktSize(ETH_DMADESCTypeDef* ptr_desc); 679 void ETH_SoftwareReset(void); 680 FlagStatus ETH_GetSoftwareResetStatus(void); 681 FlagStatus ETH_GetDMAFlagStatus(u32 flag); 682 void ETH_DMAClearFlag(u32 flag); 683 void ETH_DMAITConfig(u32 it, FunctionalState sta); 684 ITStatus ETH_GetDMAITStatus(u32 it); 685 void ETH_DMAClearITPendingBit(u32 it); 686 u32 ETH_GetTransmitProcessState(void); 687 u32 ETH_GetReceiveProcessState(void); 688 void ETH_FlushTransmitFIFO(void); 689 FlagStatus ETH_GetFlushTransmitFIFOStatus(void); 690 void ETH_DMATransmissionCmd(FunctionalState sta); 691 void ETH_DMAReceptionCmd(FunctionalState sta); 692 FlagStatus ETH_GetDMAOverflowStatus(u32 val); 693 u32 ETH_GetRxOverflowMissedFrameCounter(void); 694 u32 ETH_GetBufferUnavailableMissedFrameCounter(void); 695 u32 ETH_GetCurrentTxDescStartAddress(void); 696 u32 ETH_GetCurrentRxDescStartAddress(void); 697 u32 ETH_GetCurrentTxBufferAddress(void); 698 u32 ETH_GetCurrentRxBufferAddress(void); 699 void ETH_ResumeDMATransmission(void); 700 void ETH_ResumeDMAReception(void); 701 void ETH_SetReceiveWatchdogTimer(u8 val); 702 u16 ETH_ReadPHYRegister(u16 addr, u16 reg); 703 u16 ETH_WritePHYRegister(u16 addr, u16 reg, u16 val); 704 u32 ETH_PHYLoopBackCmd(u16 addr, FunctionalState sta); 705 void ETH_ResetWakeUpFrameFilterRegisterPointer(void); 706 void ETH_SetWakeUpFrameFilterRegister(u32* buf); 707 void ETH_GlobalUnicastWakeUpCmd(FunctionalState sta); 708 FlagStatus ETH_GetPMTFlagStatus(u32 flag); 709 void ETH_WakeUpFrameDetectionCmd(FunctionalState sta); 710 void ETH_MagicPacketDetectionCmd(FunctionalState sta); 711 void ETH_PowerDownCmd(FunctionalState sta); 712 void ETH_MMCCounterFullPreset(void); 713 void ETH_MMCCounterHalfPreset(void); 714 void ETH_MMCCounterFreezeCmd(FunctionalState sta); 715 void ETH_MMCResetOnReadCmd(FunctionalState sta); 716 void ETH_MMCCounterRolloverCmd(FunctionalState sta); 717 void ETH_MMCCountersReset(void); 718 void ETH_MMCITConfig(u32 it, FunctionalState sta); 719 ITStatus ETH_GetMMCITStatus(u32 it); 720 u32 ETH_GetMMCRegister(u32 reg); 721 722 /// @} 723 724 /// @} 725 726 /// @} 727 //////////////////////////////////////////////////////////////////////////////// 728 #endif //__HAL_ETH_H 729 //////////////////////////////////////////////////////////////////////////////// 730