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Searched refs:ETH_PHY_BASE (Results 1 – 4 of 4) sorted by relevance

/bsp/cvitek/drivers/libraries/eth/
A Deth_phy_cvitek.c64 mmio_write_32(ETH_PHY_BASE + 0x804, 0x0001); in cv181x_config()
75 mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0500); in cv181x_config()
78 mmio_write_32(ETH_PHY_BASE + 0x040, 0x0c00); in cv181x_config()
81 mmio_write_32(ETH_PHY_BASE + 0x040, 0x0c7e); in cv181x_config()
87 mmio_write_32(ETH_PHY_BASE + 0x800, 0x0906); in cv181x_config()
91 mmio_write_32(ETH_PHY_BASE + 0x07c, 0x0500); in cv181x_config()
128 mmio_write_32(ETH_PHY_BASE + 0x05c, 0x0c10); in cv181x_config()
131 mmio_write_32(ETH_PHY_BASE + 0x068, 0x0003); in cv181x_config()
134 mmio_write_32(ETH_PHY_BASE + 0x054, 0x0000); in cv181x_config()
170 mmio_write_32(ETH_PHY_BASE + 0x040, (0x0001 | mmio_read_32(ETH_PHY_BASE + 0x040))); in cv181x_config()
[all …]
A Dcvi_eth_phy.c170 val = mmio_read_32(ETH_PHY_BASE) & ETH_PHY_INIT_MASK; in eth_config()
171 mmio_write_32(ETH_PHY_BASE, (val | ETH_PHY_SHUTDOWN) & ETH_PHY_RESET); in eth_config()
173 mmio_write_32(ETH_PHY_BASE, val & ETH_PHY_POWERUP & ETH_PHY_RESET); in eth_config()
175 mmio_write_32(ETH_PHY_BASE, (val & ETH_PHY_POWERUP) | ETH_PHY_RESET_N); in eth_config()
A Dcvi_eth_phy.h352 #define ETH_PHY_BASE (uintptr_t)DRV_IOREMAP((void *)0x03009000, 0x1000) macro
/bsp/cvitek/drivers/
A Ddrv_eth.c58 mmio_write_32(ETH_PHY_BASE + 0x804, 0x0001); in cvi_ephy_id_init()
61 mmio_write_32(ETH_PHY_BASE + 0x800, 0x0900); in cvi_ephy_id_init()
64 mmio_write_32(ETH_PHY_BASE + 0x800, 0x0904); in cvi_ephy_id_init()
67 mmio_write_32(ETH_PHY_BASE + 0x008, 0x0043); in cvi_ephy_id_init()
68 mmio_write_32(ETH_PHY_BASE + 0x00c, 0x5649); in cvi_ephy_id_init()
71 mmio_write_32(ETH_PHY_BASE + 0x804, 0x0000); in cvi_ephy_id_init()

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