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Searched refs:FCR (Results 1 – 25 of 114) sorted by relevance

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/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_lcd.c348 HT_LCD->FCR = (HT_LCD->FCR & ~(15ul << 22)) | Sel; in LCD_PrescalerConfig()
376 HT_LCD->FCR = (HT_LCD->FCR & ~(15ul << 18)) | Sel; in LCD_DividerConfig()
391 HT_LCD->FCR = (HT_LCD->FCR & ~(3ul << 16)) | Sel; in LCD_BlinkModeConfig()
410 HT_LCD->FCR = (HT_LCD->FCR & ~(7ul << 13)) | Sel; in LCD_BlinkFrequencyConfig()
436 HT_LCD->FCR = (HT_LCD->FCR & ~(7ul << 10)) | Sel; in LCD_ChargePumpConfig()
455 HT_LCD->FCR = (HT_LCD->FCR & ~(7ul << 7)) | Sel; in LCD_DeadTimeConfig()
474 u32 FCR = HT_LCD->FCR; in LCD_HighDriveConfig() local
478 FCR |= (1ul << 0); in LCD_HighDriveConfig()
482 FCR &= ~(1ul << 0); in LCD_HighDriveConfig()
483 FCR = (FCR & ~(7ul << 4)) | Sel; in LCD_HighDriveConfig()
[all …]
A Dht32f5xxxx_i2s.c192 HT_I2S->FCR |= I2S_FIFO; in I2S_FIFOReset()
212 HT_I2S->FCR = ((HT_I2S->FCR & (~0x0000000F)) | I2S_FIFOLevel); in I2S_FIFOTrigLevelConfig()
216 HT_I2S->FCR = ((HT_I2S->FCR & (~0x000000F0)) | (I2S_FIFOLevel << 4)); in I2S_FIFOTrigLevelConfig()
A Dht32f5xxxx_spi.c172 SPIx->FCR = SPI_InitStruct->SPI_FIFO | SPI_InitStruct->SPI_TxFIFOTriggerLevel | in SPI_Init()
290 SPIx->FCR |= FCR_FIFOEN_SET; in SPI_FIFOCmd()
294 SPIx->FCR &= FCR_FIFOEN_RESET; in SPI_FIFOCmd()
560 SPIx->FCR = ((SPIx->FCR & (0x00000400 | (FCR_FIFO_MASK << 4))) | SPI_FIFOLevel); in SPI_FIFOTriggerLevelConfig()
564 SPIx->FCR = ((SPIx->FCR & (0x00000400 | FCR_FIFO_MASK)) | (SPI_FIFOLevel << 4)); in SPI_FIFOTriggerLevelConfig()
A Dht32f5xxxx_sled.c253 SLEDx->FCR = FifoLevel; in SLED_FIFOTrigLevelConfig()
263 return (SLEDx->FCR >> 24); in SLED_GetFIFOStatus()
276 SLEDx->FCR |= (1 << 0); in SLED_FIFOReset()
A Dht32f5xxxx_usart.c547 USARTx->FCR = (USARTx->FCR & ~(FCR_TL_Mask << (TxRx * 2))) | (USART_tl << (TxRx * 2)); in USART_TXRXTLConfig()
580 USARTx->FCR |= USART_FIFODirection; in USART_FIFOReset()
600 return (u8)((USARTx->FCR & 0xF0000) >> 16); in USART_GetFIFOStatus()
604 return (u8)((USARTx->FCR & 0xF000000) >> 24); in USART_GetFIFOStatus()
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/
A Dht32f1xxxx_i2s.c192 HT_I2S->FCR |= I2S_FIFO; in I2S_FIFOReset()
212 HT_I2S->FCR = ((HT_I2S->FCR & (~0x0000000F)) | I2S_FIFOLevel); in I2S_FIFOTrigLevelConfig()
216 HT_I2S->FCR = ((HT_I2S->FCR & (~0x000000F0)) | (I2S_FIFOLevel << 4)); in I2S_FIFOTrigLevelConfig()
A Dht32f1xxxx_spi.c143 SPIx->FCR = SPI_InitStruct->SPI_FIFO | SPI_InitStruct->SPI_TxFIFOTriggerLevel | in SPI_Init()
255 SPIx->FCR |= FCR_FIFOEN_SET; in SPI_FIFOCmd()
259 SPIx->FCR &= FCR_FIFOEN_RESET; in SPI_FIFOCmd()
521 SPIx->FCR = ((SPIx->FCR & (0x00000400 | (FCR_FIFO_MASK << 4))) | SPI_FIFOLevel); in SPI_FIFOTriggerLevelConfig()
525 SPIx->FCR = ((SPIx->FCR & (0x00000400 | FCR_FIFO_MASK)) | (SPI_FIFOLevel << 4)); in SPI_FIFOTriggerLevelConfig()
A Dht32f1xxxx_usart.c446 USARTx->FCR |= (USART_EN_ON << TxRx); in USART_TxRxCmd()
450 USARTx->FCR &= ~(USART_EN_ON << TxRx); in USART_TxRxCmd()
651 USARTx->FCR = (USARTx->FCR & ~(FCR_TL_Mask << (TxRx * 2))) | (USART_tl << (TxRx * 2)); in USART_TXRXTLConfig()
688 USARTx->FCR |= USART_FIFODirection; in USART_FIFOReset()
718 return (u8)((USARTx->FCR & 0xF0000) >> 16); in USART_GetFIFOStatus()
722 return (u8)((USARTx->FCR & 0xF000000) >> 24); in USART_GetFIFOStatus()
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/
A Dtae32f53xx_ll_fpll.h55 #define __LL_FPLL_En(__FPLL__) SET_BIT((__FPLL__)->FCR, FPLL_EN_Msk)
62 #define __LL_FPLL_Dis(__FPLL__) CLEAR_BIT((__FPLL__)->FCR, FPLL_EN_Msk)
69 #define __LL_FPLL_Start(__FPLL__) SET_BIT((__FPLL__)->FCR, FPLL_START_Msk)
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_hal_lcd.h515 SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
521 CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
543 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
564 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
585 MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \
613 …MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BL…
627 SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
632 CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
647 #define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/
A Dald_qspi.c632 SET_BIT(hperh->perh->FCR, QSPI_FCR_WREN_MSK); in ald_qspi_execute_stig_cmd()
640 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_WDNUM_MSK); in ald_qspi_execute_stig_cmd()
641 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_WREN_MSK); in ald_qspi_execute_stig_cmd()
645 SET_BIT(hperh->perh->FCR, QSPI_FCR_ADDREN_MSK); in ald_qspi_execute_stig_cmd()
651 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_ADNUM_MSK); in ald_qspi_execute_stig_cmd()
656 SET_BIT(hperh->perh->FCR, QSPI_FCR_MODBEN_MSK); in ald_qspi_execute_stig_cmd()
664 SET_BIT(hperh->perh->FCR, QSPI_FCR_RDEN_MSK); in ald_qspi_execute_stig_cmd()
667 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_RDEN_MSK); in ald_qspi_execute_stig_cmd()
668 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_RDNUM_MSK); in ald_qspi_execute_stig_cmd()
672 SET_BIT(hperh->perh->FCR, QSPI_FCR_CMDT_MSK); in ald_qspi_execute_stig_cmd()
[all …]
/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/
A Dald_uart.c324 WRITE_REG(hperh->perh->FCR, 0x0); in ald_uart_reset()
365 SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); in ald_uart_init()
366 SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); in ald_uart_init()
367 SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); in ald_uart_init()
368 MODIFY_REG(hperh->perh->FCR, UART_FCR_RXTL_MSK, 0 << UART_FCR_RXTL_POSS); in ald_uart_init()
369 MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, 0 << UART_FCR_TXTL_POSS); in ald_uart_init()
968 SET_BIT(hperh->perh->FCR, UART_FCR_TFRST_MSK); in ald_uart_tx_fifo_config()
969 MODIFY_REG(hperh->perh->FCR, UART_FCR_TXTL_MSK, config << UART_FCR_TXTL_POSS); in ald_uart_tx_fifo_config()
970 SET_BIT(hperh->perh->FCR, UART_FCR_FIFOEN_MSK); in ald_uart_tx_fifo_config()
986 SET_BIT(hperh->perh->FCR, UART_FCR_RFRST_MSK); in ald_uart_rx_fifo_config()
[all …]
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/
A Ddw_uart_ll.h284 __OM uint32_t FCR; /* Offset: 0x008 ( /W) FIFO control register */ member
317 uart_base->FCR = UART_FIFO_INIT_CONFIG; in dw_uart_fifo_init()
322 uart_base->FCR |= DW_UART_FCR_FIFOE_EN; in dw_uart_fifo_enable()
327 uart_base->FCR &= ~(DW_UART_FCR_FIFOE_EN); in dw_uart_fifo_disable()
393 uart_base->FCR = value; in dw_uart_set_fcr_reg()
/bsp/airm2m/air105/libraries/HAL_Driver/Src/
A Dcore_spi.c199 …SPI->FCR = (63 << HSPIM_FCR_PARAM_TRANSIMIT_FIFO_EMPTY_THRESHOULD_POS)|(0 << HSPIM_FCR_PARAM_RECEI… in HSPI_IrqHandle()
206 …SPI->FCR = (63 << HSPIM_FCR_PARAM_TRANSIMIT_FIFO_EMPTY_THRESHOULD_POS)|(0 << HSPIM_FCR_PARAM_RECEI… in HSPI_IrqHandle()
514 …SPI->FCR = (32 << HSPIM_FCR_PARAM_TRANSIMIT_FIFO_EMPTY_THRESHOULD_POS)|(0 << HSPIM_FCR_PARAM_RECEI… in HSPI_Transfer()
515 SPI->FCR &= ~(3 << 6); in HSPI_Transfer()
539 SPI->FCR &= ~(3 << 6); in HSPI_Transfer()
641 …HSPI->FCR = (32 << HSPIM_FCR_PARAM_TRANSIMIT_FIFO_EMPTY_THRESHOULD_POS)|(32 << HSPIM_FCR_PARAM_REC… in prvSPI_BlockTransfer()
642 HSPI->FCR &= ~(3 << 6); in prvSPI_BlockTransfer()
813 …HSPI->FCR = (32 << HSPIM_FCR_PARAM_TRANSIMIT_FIFO_EMPTY_THRESHOULD_POS)|(32 << HSPIM_FCR_PARAM_REC… in prvSPI_FlashBlockTransfer()
814 HSPI->FCR &= ~(3 << 6); in prvSPI_FlashBlockTransfer()
1064 …HSPI->FCR = (32 << HSPIM_FCR_PARAM_TRANSIMIT_FIFO_EMPTY_THRESHOULD_POS)|(32 << HSPIM_FCR_PARAM_REC… in SPI_TransferStop()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_uart_drv.h275 ptr->FCR = UART_FCR_TFIFORST_MASK | (ptr->GPR); in uart_reset_tx_fifo()
289 ptr->FCR = UART_FCR_RFIFORST_MASK | (ptr->GPR); in uart_reset_rx_fifo()
303 ptr->FCR = UART_FCR_RFIFORST_MASK | UART_FCR_TFIFORST_MASK | (ptr->GPR); in uart_reset_all_fifo()
473 ptr->FCR = ptr->GPR; in uart_clear_rxline_idle_flag()
/bsp/avr32/software_framework/drivers/flashc/
A Dflashc.c50 avr32_flashc_fcr_t FCR; member
148 u_avr32_flashc_fcr.FCR.fws = wait_state; in flashc_set_wait_state()
173 u_avr32_flashc_fcr.FCR.frdy = (enable != false); in flashc_enable_ready_int()
187 u_avr32_flashc_fcr.FCR.locke = (enable != false); in flashc_enable_lock_error_int()
201 u_avr32_flashc_fcr.FCR.proge = (enable != false); in flashc_enable_prog_error_int()
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_uart_drv.c174 ptr->FCR = UART_FCR_TFIFORST_MASK | UART_FCR_RFIFORST_MASK; in uart_init()
180 ptr->FCR = tmp; in uart_init()
379 ptr->FCR = UART_FCR_TFIFOT_SET(ctrl->tx_fifo_level) in uart_config_fifo_ctrl()
/bsp/rv32m1_vega/rv32m1_sdk_riscv/devices/RV32M1/drivers/
A Dfsl_lpspi.c876 …base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTi… in LPSPI_MasterTransferNonBlocking()
1061 base->FCR = in LPSPI_MasterTransferHandleIRQ()
1062 (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | in LPSPI_MasterTransferHandleIRQ()
1245 …base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTi… in LPSPI_SlaveTransferNonBlocking()
1429 base->FCR = in LPSPI_SlaveTransferHandleIRQ()
1430 (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | in LPSPI_SlaveTransferHandleIRQ()
A Dfsl_dac.c93 base->FCR = LPDAC_FCR_WML(config->fifoWatermarkLevel); in DAC_Init()
/bsp/smartfusion2/libraries/mss_uart/
A Dmss_uart.c542 this_uart->hw_reg->FCR = (this_uart->hw_reg->FCR & in MSS_UART_set_rx_handler()
1332 ((MSS_UART_READY_MODE0 == mode) ? clear_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) : in MSS_UART_set_ready_mode()
1333 set_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) ); in MSS_UART_set_ready_mode()
1500 this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE; in global_init()
1502 set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_RX_FIFO); in global_init()
1504 set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_TX_FIFO); in global_init()
1509 set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN); in global_init()
/bsp/nxp/lpc/lpc176x/drivers/
A Duart.c135 LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ in rt_uart_init()
168 LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */ in rt_uart_init()
/bsp/ck802/libraries/common/usart/
A Ddw_usart.h93 __OM uint32_t FCR; /* Offset: 0x008 ( /W) FIFO control register */ member
/bsp/nxp/lpc/lpc178x/drivers/
A Dlpc177x_8x_uart.c213 UARTx->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS); in UART_Init()
216 UARTx->FCR = 0; in UART_Init()
857 ((LPC_UART1_TypeDef *)UARTx)->FCR = tmp & UART_FCR_BITMASK; in UART_FIFOConfig()
861 UARTx->FCR = tmp & UART_FCR_BITMASK; in UART_FIFOConfig()
/bsp/wch/risc-v/Libraries/ch56x_drivers/
A Dch56x_uart.c153 uxreg->FCR.reg = fcr.reg; in uart_configure()
175 uxreg->FCR.fifo_trig = UART_1BYTE_TRIG; in uart_control()
/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_uart.c168 pReg->FCR = UART_FCR_ENABLE_FIFO; in HAL_UART_Resume()
365 pReg->FCR = in HAL_UART_Init()

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