1 /* 2 * Copyright (C) 2018 ETH Zurich and University of Bologna 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 * 16 * SPDX-License-Identifier: Apache-2.0 17 */ 18 19 20 #ifndef HAL_INCLUDE_HAL_FLL_H_ 21 #define HAL_INCLUDE_HAL_FLL_H_ 22 23 #define FLL_STATUS_OFFSET 0x000 24 #define FLL_CONF1_OFFSET 0x004 25 #define FLL_CONF2_OFFSET 0x008 26 #define FLL_INTEGRATOR_OFFSET 0x00C 27 28 #define FLL_STATUS_MULT_FACTOR_BIT 0 29 #define FLL_STATUS_MULT_FACTOR_WIDTH 16 30 #define FLL_STATUS_MULT_FACTOR_MASK (0xFFFF) 31 32 #define FLL_CONF1_MODE_BIT 31 33 #define FLL_CONF1_MODE_WIDTH 1 34 #define FLL_CONF1_MODE_MASK (0x80000000) 35 36 #define FLL_CONF1_LOCK_BIT 30 37 #define FLL_CONF1_LOCK_WIDTH 1 38 #define FLL_CONF1_LOCK_MASK (0x40000000) 39 40 #define FLL_CONF1_DIV_BIT 26 41 #define FLL_CONF1_DIV_WIDTH 4 42 #define FLL_CONF1_DIV_MASK (0x3C000000) 43 44 #define FLL_CONF1_DCO_BIT 16 45 #define FLL_CONF1_DCO_WIDTH 10 46 #define FLL_CONF1_DCO_MASK (0x03FF0000) 47 48 #define FLL_CONF1_MULT_FACTOR_BIT 0 49 #define FLL_CONF1_MULT_FACTOR_WIDTH 16 50 #define FLL_CONF1_MULT_FACTOR_MASK (0xFFFF) 51 52 #define FLL_CONF1_MODE_STANDALONE 0 53 #define FLL_CONF1_MODE_NORMAL 1 54 55 #define FLL_CONF2_GAIN_BIT 0 56 #define FLL_CONF2_GAIN_WIDTH 4 57 #define FLL_CONF2_GAIN_MASK (0x0000000F) 58 59 #define FLL_CONF2_DEASSERT_CYCLES_BIT 4 60 #define FLL_CONF2_DEASSERT_CYCLES_WIDTH 6 61 #define FLL_CONF2_DEASSERT_CYCLES_MASK (0x000003F0) 62 63 #define FLL_CONF2_ASSERT_CYCLES_BIT 10 64 #define FLL_CONF2_ASSERT_CYCLES_WIDTH 6 65 #define FLL_CONF2_ASSERT_CYCLES_MASK (0x0000FC00) 66 67 #define FLL_CONF2_TOLERANCE_BIT 16 68 #define FLL_CONF2_TOLERANCE_WIDTH 12 69 #define FLL_CONF2_TOLERANCE_MASK (0x0FFF0000) 70 71 #define FLL_CONF2_STA_CLOCK_BIT 29 72 #define FLL_CONF2_STA_CLOCK_WIDTH 1 73 #define FLL_CONF2_STA_CLOCK_MASK (0x20000000) 74 75 #define FLL_CONF2_OPEN_LOOP_BIT 30 76 #define FLL_CONF2_OPEN_LOOP_WIDTH 1 77 #define FLL_CONF2_OPEN_LOOP_MASK (0x40000000) 78 79 #define FLL_CONF2_DITHERING_BIT 31 80 #define FLL_CONF2_DITHERING_WIDTH 1 81 #define FLL_CONF2_DITHERING_MASK (0x80000000) 82 83 #define FLL_INTEGRATOR_INT_BIT 16 84 #define FLL_INTEGRATOR_INT_WIDTH 10 85 #define FLL_INTEGRATOR_INT_MASK (0x03FF0000) 86 87 #define FLL_INTEGRATOR_FRACT_BIT 6 88 #define FLL_INTEGRATOR_FRACT_WIDTH 10 89 #define FLL_INTEGRATOR_FRACT_MASK (0x0000FFC0) 90 91 #if !defined(LANGUAGE_ASSEMBLY) && !defined(_ASMLANGUAGE) 92 93 typedef union { 94 struct { 95 unsigned int actual_mult_factor:16; /* Fll current multiplication factor */ 96 unsigned int reserved:16; 97 }; 98 unsigned int raw; 99 } fll_reg_status_t; 100 101 typedef union { 102 struct { 103 unsigned int mult_factor:16; /* Fll requested multiplication factor, reset: 0x5f5. 104 If RefClk=32768 and Div=2 Freq= 24.98 MHz */ 105 unsigned int dco_input:10; /* DCO input code for stand alone mode, reset: 0x121 */ 106 unsigned int clock_out_divider:4; /* Fll clock output divider, reset: 0x1 e.g div 2 */ 107 unsigned int output_lock_enable:1;/* Fll output gated by lock signal (active high), reset 1 */ 108 unsigned int mode:1; /* Fll mode. 0: stand alone (unlocked), 1: normal, reset 0 */ 109 }; 110 unsigned int raw; 111 } fll_reg_conf1_t; 112 113 typedef union { 114 struct { 115 unsigned int loop_gain:4; /* Fll loop gain, reset: 0x9 */ 116 unsigned int de_assert_cycles:6; /* Normal mode: number of refclock unstable cycles till lock de-assert 117 Standalone mode: lower 6 bits of lock assert counter. Reset: 0x10 */ 118 unsigned int assert_cycles:6; /* Normal mode: number of refclock stable cycles till lock assert 119 Standalone mode: upper 6 bits of lock assert counter. Reset: 0x10 */ 120 unsigned int lock_tolerance:12; /* Lock tolerance: margin arounf the target mult factor where clock is 121 considered as stable. Reset: 0x200 122 With Fmax=250Mhw (Div=2^4), Fmin=32K (Div=2^15) 123 Tolerance: 32K*(512/16)=1.048MHz .. 512 Hz */ 124 unsigned int pad:1; 125 unsigned int config_clock_sel:1; /* Select ref clock when mode = standalone, 0:RefClock, 1: DcoOut. Reset:1 */ 126 unsigned int open_loop:1; /* When 1 clock operates in open loop when locked */ 127 unsigned int dithering:1; /* When 1 Dithering is enabled */ 128 }; 129 unsigned int raw; 130 } fll_reg_conf2_t; 131 132 typedef union { 133 struct { 134 unsigned int pad1:6; 135 unsigned int state_fract_part:10; /* Integrator state: fractional part (dithering input unit) */ 136 unsigned int state_int_part:10; /* Integratot state: integer part (DCO input bits) */ 137 unsigned int pad2:6; 138 }; 139 unsigned int raw; 140 } fll_reg_integrator_t; 141 142 #endif 143 144 145 146 #define FLL_STATUS_MULT_FACTOR_GET(value) ((((unsigned int)(value)) >> 0) & 0xFFFF) 147 #define FLL_STATUS_MULT_FACTOR_SET(dst,src,factor) (__BITINSERT((dst),(src),16,0)) 148 #define FLL_STATUS_MULT_FACTOR(factor) ((factor) << 16) 149 150 151 #define FLL_CONF1_MODE_GET(value) ((((unsigned int)(value)) >> 16) & 0x1) 152 #define FLL_CONF1_MODE_SET(dst,src) (__BITINSERT((dst),(src),1,31)) 153 #define FLL_CONF1_MODE(factor) ((factor) << 31) 154 155 #define FLL_CONF1_LOCK_GET(value) ((((unsigned int)(value)) >> 16) & 0x1) 156 #define FLL_CONF1_LOCK_SET(dst,src) (__BITINSERT((dst),(src),30,1)) 157 #define FLL_CONF1_LOCK(factor) ((factor) << 30) 158 159 #define FLL_CONF1_DIV_GET(value) ((((unsigned int)(value)) >> 26) & 0xF) 160 #define FLL_CONF1_DIV_SET(dst,src) (__BITINSERT((dst),(src),26,4)) 161 #define FLL_CONF1_DIV(factor) ((factor) << 26) 162 163 #define FLL_CONF1_DCO_GET(value) ((((unsigned int)(value)) >> 16) & 0x3FF) 164 #define FLL_CONF1_DCO_SET(dst,src) (__BITINSERT((dst),(src),16,10)) 165 #define FLL_CONF1_DCO(factor) ((factor) << 16) 166 167 #define FLL_CONF1_MULT_FACTOR_GET(value) ((((unsigned int)(value)) >> 0) &0xFFFF) 168 #define FLL_CONF1_MULT_FACTOR_SET(dst,src) (__BITINSERT((dst),(src),0,16)) 169 #define FLL_CONF1_MULT_FACTOR(factor) ((factor) << 0) 170 171 #define FLL_CONF2_GAIN_GET(value) ((((unsigned int)(value)) >> 0) & 0xF) 172 #define FLL_CONF2_GAIN_SET(dst,src) (__BITINSERT((dst),(src),4,0)) 173 #define FLL_CONF2_GAIN(value) ((value) << 0) 174 175 #define FLL_CONF2_ASSERT_CYCLES_GET(value) ((((unsigned int)(value)) >> 4) & 0x3F) 176 #define FLL_CONF2_ASSERT_CYCLES_SET(dst,src) (__BITINSERT((dst),(src),6,4)) 177 #define FLL_CONF2_ASSERT_CYCLES(value) ((value) << 4) 178 179 #define FLL_CONF2_DEASSERT_CYCLES_GET(value) ((((unsigned int)(value)) >> 10) & 0x3F) 180 #define FLL_CONF2_DEASSERT_CYCLES_SET(dst,src) (__BITINSERT((dst),(src),6,10)) 181 #define FLL_CONF2_DEASSERT_CYCLES(value) ((value) << 10) 182 183 #define FLL_CONF2_TOLERANCE_GET(value) ((((unsigned int)(value)) >> 16) & 0xFFF) 184 #define FLL_CONF2_TOLERANCE_SET(dst,src) (__BITINSERT((dst),(src),12,16)) 185 #define FLL_CONF2_TOLERANCE(value) ((value) << 16) 186 187 #define FLL_CONF2_STA_CLOCK_GET(value) ((((unsigned int)(value)) >> 29) & 0x1) 188 #define FLL_CONF2_STA_CLOCK_SET(dst,src) (__BITINSERT((dst),(src),1,29)) 189 #define FLL_CONF2_STA_CLOCK(value) ((value) << 29) 190 191 #define FLL_CONF2_OPEN_LOOP_GET(value) ((((unsigned int)(value)) >> 30) & 0x1) 192 #define FLL_CONF2_OPEN_LOOP_SET(dst,src) (__BITINSERT((dst),(src),1,30)) 193 #define FLL_CONF2_OPEN_LOOP(value) ((value) << 30) 194 195 #define FLL_CONF2_DITHER_GET(value) ((((unsigned int)(value)) >> 31) & 0x1) 196 #define FLL_CONF2_DITHER_SET(dst,src) (__BITINSERT((dst),(src),1,31)) 197 #define FLL_CONF2_DITHER(value) ((value) << 31) 198 199 #define FLL_INTEGRATOR_FRACT_GET(value) ((((unsigned int)(value)) >> 6) & 0x3FF) 200 #define FLL_INTEGRATOR_FRACT_SET(dst,src) (__BITINSERT((dst),(src),6,10)) 201 #define FLL_INTEGRATOR_FRACT(value) ((value) << 6) 202 203 #define FLL_INTEGRATOR_INT_GET(value) ((((unsigned int)(value)) >> 16) & 0x3FF) 204 #define FLL_INTEGRATOR_INT_SET(dst,src) (__BITINSERT((dst),(src),16,10)) 205 #define FLL_INTEGRATOR_INT(value) ((value) << 16) 206 207 /* Maximum Log2(DCO Frequency) */ 208 #define FLL_LOG2_MAXDCO 29 209 /* Maximum Log2(Clok Divider) */ 210 #define FLL_LOG2_MAXDIV 15 211 /* Maximum Log2(Multiplier) */ 212 #define FLL_LOG2_MAXM (FLL_LOG2_MAXDCO - ARCHI_REF_CLOCK_LOG2) 213 214 /* TODO: doc */ 215 void pulp_fll_init(void); 216 unsigned int __fll_init(int fll); 217 unsigned int __rt_fll_set_freq(int fll, unsigned int frequency); 218 219 #endif /* HAL_INCLUDE_HAL_FLL_H_ */ 220