1 /**
2 *******************************************************************************************************
3 * @file fm33lc0xx_fl_dma.h
4 * @author FMSH Application Team
5 * @brief Head file of DMA FL Module
6 *******************************************************************************************************
7 * @attention
8 *
9 * Copyright (c) [2021] [Fudan Microelectronics]
10 * THIS SOFTWARE is licensed under Mulan PSL v2.
11 * You can use this software according to the terms and conditions of the Mulan PSL v2.
12 * You may obtain a copy of Mulan PSL v2 at:
13 * http://license.coscl.org.cn/MulanPSL2
14 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
15 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
16 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
17 * See the Mulan PSL v2 for more details.
18 *
19 *******************************************************************************************************
20 */
21 /********************************************DMA channel mapping*****************************************
22 -------------------------------------------------------------------------------------------------
23 |Channel| 0 | 1 | 2 | 3 | 4 | 5 | 6 |
24 --------------------------------------------------------------------------------------------------
25 |Func1 |ADC |UARTRX0 | SPI2RX |SPI1_RX |ADC |SPI1RX |SPI1TX |
26 -----------------------------------------------------------------------------------------
27 |Func2 |LPUART0RX|LPUART0TX| UARTTX0 |UARTRX0 |SPI1TX |SPI2RX |SPI2TX |
28 --------------------------------------------------------------------------------------------------
29 |Func3 |LPUART1TX|IICRX | UARTRX4 |UARTRX1 |SPI2TX |UARTRX1 |UARTTX1 |
30 --------------------------------------------------------------------------------------------------
31 |Func4 |AESIN |AESOUT | LPUART1RX|UARTTX4 |UARTTX0 |LPUART0TX |UARTTX5 |
32 --------------------------------------------------------------------------------------------------
33 |Func5 |CRC |ATIMCH2 | I2CTX |LPUART0RX|UARTTX1 |LPUART1RX |LPUART1TX |
34 --------------------------------------------------------------------------------------------------
35 |Func6 |ATIMCH1 |GTIM0CH2 | ATIMCH3 |ATIMCH4 |UARTRX5 |U7816RX |U7816TX |
36 --------------------------------------------------------------------------------------------------
37 |Func7 |GTIM0CH1 |GTIM1CH2 | GTIM0CH3 |GTIM0CH4 |I2CRX |GTIM1TRIG/UEV |I2CTX |
38 --------------------------------------------------------------------------------------------------
39 |Func8 |GTIM1CH1 |LPT32CH1 | GTIM1CH3 |GTIM1CH4 |ATIMTRIG/COM/UEV |LPT32CH2 |GTIM0TRIG\UEV |
40 --------------------------------------------------------------------------------------------------
41 --------------------------------------------------------------------------------------------------
42 ********************************************DMA channel mapping*****************************************/
43
44
45 /* Define to prevent recursive inclusion---------------------------------------------------------------*/
46 #ifndef __FM33LC0XX_FL_DMA_H
47 #define __FM33LC0XX_FL_DMA_H
48
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 /* Includes -------------------------------------------------------------------------------------------*/
53 #include "fm33lc0xx_fl_def.h"
54 /** @addtogroup FM33LC0XX_FL_Driver
55 * @{
56 */
57
58 /** @defgroup DMA DMA
59 * @brief DMA FL driver
60 * @{
61 */
62
63 /* Exported types -------------------------------------------------------------------------------------*/
64 /** @defgroup DMA_FL_ES_INIT DMA Exported Init structures
65 * @{
66 */
67
68 /**
69 * @brief FL DMA Init Sturcture definition
70 */
71 typedef struct
72 {
73 /*! DMA外设映射地址 */
74 uint32_t periphAddress;
75
76 /*! DMA传输方向 */
77 uint32_t direction;
78
79 /*! RAM地址增长方向 */
80 uint32_t memoryAddressIncMode;
81
82 /*! RAM地址增长方向 */
83 uint32_t flashAddressIncMode;
84
85 /*! DAM传输通道数据位宽 */
86 uint32_t dataSize;
87
88 /*! DMA通道优先级 */
89 uint32_t priority;
90
91 /*! 循环模式使能 */
92 uint32_t circMode;
93
94 } FL_DMA_InitTypeDef;
95
96 /**
97 * @brief FL DMA Config Sturcture definition
98 */
99 typedef struct
100 {
101 /* DMA传输RAM地址 */
102 uint32_t memoryAddress;
103
104 /* DMA传输请求次数 */
105 uint32_t transmissionCount;
106
107 } FL_DMA_ConfigTypeDef;
108
109 /**
110 * @brief Configuration with temporary structure variable users will not be used directly
111 */
112 typedef struct
113 {
114 __IO uint32_t CHCR;
115 __IO uint32_t CHMAD;
116 } CHANNEL;
117
118 /**
119 * @brief Configuration with temporary structure variable users will not be used directly
120 */
121 typedef struct
122 {
123 __IO uint32_t RESV;
124 __IO CHANNEL Channel[7];
125 __IO uint32_t CH7CR;
126 __IO uint32_t CH7FLSAD;
127 __IO uint32_t CH7MAD;
128 } DMA_ADDR;
129
130 /**
131 * @}
132 */
133 /* Exported constants ---------------------------------------------------------------------------------*/
134 /** @defgroup DMA_FL_Exported_Constants DMA Exported Constants
135 * @{
136 */
137
138 #define DMA_GCR_ADDRERR_IE_Pos (1U)
139 #define DMA_GCR_ADDRERR_IE_Msk (0x1U << DMA_GCR_ADDRERR_IE_Pos)
140 #define DMA_GCR_ADDRERR_IE DMA_GCR_ADDRERR_IE_Msk
141
142 #define DMA_GCR_EN_Pos (0U)
143 #define DMA_GCR_EN_Msk (0x1U << DMA_GCR_EN_Pos)
144 #define DMA_GCR_EN DMA_GCR_EN_Msk
145
146 #define DMA_CHCR_TSIZE_Pos (16U)
147 #define DMA_CHCR_TSIZE_Msk (0xffffU << DMA_CHCR_TSIZE_Pos)
148 #define DMA_CHCR_TSIZE DMA_CHCR_TSIZE_Msk
149
150 #define DMA_CHCR_PRI_Pos (12U)
151 #define DMA_CHCR_PRI_Msk (0x3U << DMA_CHCR_PRI_Pos)
152 #define DMA_CHCR_PRI DMA_CHCR_PRI_Msk
153
154 #define DMA_CHCR_INC_Pos (11U)
155 #define DMA_CHCR_INC_Msk (0x1U << DMA_CHCR_INC_Pos)
156 #define DMA_CHCR_INC DMA_CHCR_INC_Msk
157
158 #define DMA_CH7CR_MEMORY_INC_Pos (9U)
159 #define DMA_CH7CR_MEMORY_INC_Msk (0x1U << DMA_CH7CR_MEMORY_INC_Pos)
160 #define DMA_CH7CR_MEMORY_INC DMA_CH7CR_MEMORY_INC_Msk
161
162 #define DMA_CH7CR_FLASH_INC_Pos (8U)
163 #define DMA_CH7CR_FLASH_INC_Msk (0x1U << DMA_CH7CR_FLASH_INC_Pos)
164 #define DMA_CH7CR_FLASH_INC DMA_CH7CR_FLASH_INC_Msk
165
166 #define DMA_CHCR_SSEL_Pos (8U)
167 #define DMA_CHCR_SSEL_Msk (0x7U << DMA_CHCR_SSEL_Pos)
168 #define DMA_CHCR_SSEL DMA_CHCR_SSEL_Msk
169
170 #define DMA_CHCR_DIR_Pos (6U)
171 #define DMA_CHCR_DIR_Msk (0x1U << DMA_CHCR_DIR_Pos)
172 #define DMA_CHCR_DIR DMA_CHCR_DIR_Msk
173
174 #define DMA_CH7CR_DIR_Pos (10U)
175 #define DMA_CH7CR_DIR_Msk (0x1U << DMA_CH7CR_DIR_Pos)
176 #define DMA_CH7CR_DIR DMA_CH7CR_DIR_Msk
177
178 #define DMA_CHCR_BDW_Pos (4U)
179 #define DMA_CHCR_BDW_Msk (0x3U << DMA_CHCR_BDW_Pos)
180 #define DMA_CHCR_BDW DMA_CHCR_BDW_Msk
181
182 #define DMA_CHCR_CIRC_Pos (3U)
183 #define DMA_CHCR_CIRC_Msk (0x1U << DMA_CHCR_CIRC_Pos)
184 #define DMA_CHCR_CIRC DMA_CHCR_CIRC_Msk
185
186 #define DMA_CHCR_FTIE_Pos (2U)
187 #define DMA_CHCR_FTIE_Msk (0x1U << DMA_CHCR_FTIE_Pos)
188 #define DMA_CHCR_FTIE DMA_CHCR_FTIE_Msk
189
190 #define DMA_CHCR_HTIE_Pos (1U)
191 #define DMA_CHCR_HTIE_Msk (0x1U << DMA_CHCR_HTIE_Pos)
192 #define DMA_CHCR_HTIE DMA_CHCR_HTIE_Msk
193
194 #define DMA_CHCR_EN_Pos (0U)
195 #define DMA_CHCR_EN_Msk (0x1U << DMA_CHCR_EN_Pos)
196 #define DMA_CHCR_EN DMA_CHCR_EN_Msk
197
198 #define DMA_ISR_ADDRERR_Pos (16U)
199 #define DMA_ISR_ADDRERR_Msk (0x1U << DMA_ISR_ADDRERR_Pos)
200 #define DMA_ISR_ADDRERR DMA_ISR_ADDRERR_Msk
201
202 #define DMA_ISR_CHFT_Pos (8U)
203 #define DMA_ISR_CHFT_Msk (0x1U << DMA_ISR_CHFT_Pos)
204 #define DMA_ISR_CHFT DMA_ISR_CHFT_Msk
205
206 #define DMA_ISR_CHHT_Pos (0U)
207 #define DMA_ISR_CHHT_Msk (0x1U << DMA_ISR_CHHT_Pos)
208 #define DMA_ISR_CHHT DMA_ISR_CHHT_Msk
209
210
211
212 #define FL_DMA_CHANNEL_0 (0x0U << 0U)
213 #define FL_DMA_CHANNEL_1 (0x1U << 0U)
214 #define FL_DMA_CHANNEL_2 (0x2U << 0U)
215 #define FL_DMA_CHANNEL_3 (0x3U << 0U)
216 #define FL_DMA_CHANNEL_4 (0x4U << 0U)
217 #define FL_DMA_CHANNEL_5 (0x5U << 0U)
218 #define FL_DMA_CHANNEL_6 (0x6U << 0U)
219 #define FL_DMA_CHANNEL_7 (0x7U << 0U)
220
221
222
223 #define FL_DMA_PRIORITY_LOW (0x0U << DMA_CHCR_PRI_Pos)
224 #define FL_DMA_PRIORITY_MEDIUM (0x1U << DMA_CHCR_PRI_Pos)
225 #define FL_DMA_PRIORITY_HIGH (0x2U << DMA_CHCR_PRI_Pos)
226 #define FL_DMA_PRIORITY_VERYHIGH (0x3U << DMA_CHCR_PRI_Pos)
227
228
229 #define FL_DMA_MEMORY_INC_MODE_INCREASE (0x1U << DMA_CHCR_INC_Pos)
230 #define FL_DMA_MEMORY_INC_MODE_DECREASE (0x0U << DMA_CHCR_INC_Pos)
231 #define FL_DMA_CH7_MEMORY_INC_MODE_INCREASE (0x1U << DMA_CH7CR_MEMORY_INC_Pos)
232 #define FL_DMA_CH7_MEMORY_INC_MODE_DECREASE (0x0U << DMA_CH7CR_MEMORY_INC_Pos)
233 #define FL_DMA_CH7_FLASH_INC_MODE_INCREASE (0x1U << DMA_CH7CR_FLASH_INC_Pos)
234 #define FL_DMA_CH7_FLASH_INC_MODE_DECREASE (0x0U << DMA_CH7CR_FLASH_INC_Pos)
235
236
237 #define FL_DMA_FLASH_INC_MODE_INCREASE (0x1U << DMA_CH7CR_FLASH_INC_Pos)
238 #define FL_DMA_FLASH_INC_MODE_DECREASE (0x0U << DMA_CH7CR_FLASH_INC_Pos)
239
240
241 #define FL_DMA_PERIPHERAL_FUNCTION1 (0x0U << DMA_CHCR_SSEL_Pos)
242 #define FL_DMA_PERIPHERAL_FUNCTION2 (0x1U << DMA_CHCR_SSEL_Pos)
243 #define FL_DMA_PERIPHERAL_FUNCTION3 (0x2U << DMA_CHCR_SSEL_Pos)
244 #define FL_DMA_PERIPHERAL_FUNCTION4 (0x3U << DMA_CHCR_SSEL_Pos)
245 #define FL_DMA_PERIPHERAL_FUNCTION5 (0x4U << DMA_CHCR_SSEL_Pos)
246 #define FL_DMA_PERIPHERAL_FUNCTION6 (0x5U << DMA_CHCR_SSEL_Pos)
247 #define FL_DMA_PERIPHERAL_FUNCTION7 (0x6U << DMA_CHCR_SSEL_Pos)
248 #define FL_DMA_PERIPHERAL_FUNCTION8 (0x7U << DMA_CHCR_SSEL_Pos)
249
250
251 #define FL_DMA_DIR_PERIPHERAL_TO_RAM (0x0U << DMA_CHCR_DIR_Pos)
252 #define FL_DMA_DIR_RAM_TO_PERIPHERAL (0x1U << DMA_CHCR_DIR_Pos)
253 #define FL_DMA_DIR_FLASH_TO_RAM (0x1U << DMA_CH7CR_DIR_Pos)
254 #define FL_DMA_DIR_RAM_TO_FLASH (0x0U << DMA_CH7CR_DIR_Pos)
255
256
257 #define FL_DMA_BANDWIDTH_8B (0x0U << DMA_CHCR_BDW_Pos)
258 #define FL_DMA_BANDWIDTH_16B (0x1U << DMA_CHCR_BDW_Pos)
259 #define FL_DMA_BANDWIDTH_32B (0x2U << DMA_CHCR_BDW_Pos)
260
261
262 /**
263 * @}
264 */
265 /* Exported functions ---------------------------------------------------------------------------------*/
266 /** @defgroup DMA_FL_Exported_Functions DMA Exported Functions
267 * @{
268 */
269
270 /**
271 * @brief DMA address error interrupt enable
272 * @rmtoll GCR ADDRERR_IE FL_DMA_EnableIT_AddressError
273 * @param DMAx DMA instance
274 * @retval None
275 */
FL_DMA_EnableIT_AddressError(DMA_Type * DMAx)276 __STATIC_INLINE void FL_DMA_EnableIT_AddressError(DMA_Type *DMAx)
277 {
278 SET_BIT(DMAx->GCR, DMA_GCR_ADDRERR_IE_Msk);
279 }
280
281 /**
282 * @brief Get DMA address error interrupt enable status
283 * @rmtoll GCR ADDRERR_IE FL_DMA_IsEnabledIT_AddressError
284 * @param DMAx DMA instance
285 * @retval State of bit (1 or 0).
286 */
FL_DMA_IsEnabledIT_AddressError(DMA_Type * DMAx)287 __STATIC_INLINE uint32_t FL_DMA_IsEnabledIT_AddressError(DMA_Type *DMAx)
288 {
289 return (uint32_t)(READ_BIT(DMAx->GCR, DMA_GCR_ADDRERR_IE_Msk) == DMA_GCR_ADDRERR_IE_Msk);
290 }
291
292 /**
293 * @brief DMA address error interrupt disable
294 * @rmtoll GCR ADDRERR_IE FL_DMA_DisableIT_AddressError
295 * @param DMAx DMA instance
296 * @retval None
297 */
FL_DMA_DisableIT_AddressError(DMA_Type * DMAx)298 __STATIC_INLINE void FL_DMA_DisableIT_AddressError(DMA_Type *DMAx)
299 {
300 CLEAR_BIT(DMAx->GCR, DMA_GCR_ADDRERR_IE_Msk);
301 }
302
303 /**
304 * @brief DMA enable
305 * @rmtoll GCR EN FL_DMA_Enable
306 * @param DMAx DMA instance
307 * @retval None
308 */
FL_DMA_Enable(DMA_Type * DMAx)309 __STATIC_INLINE void FL_DMA_Enable(DMA_Type *DMAx)
310 {
311 SET_BIT(DMAx->GCR, DMA_GCR_EN_Msk);
312 }
313
314 /**
315 * @brief Get DMA enable status
316 * @rmtoll GCR EN FL_DMA_IsEnabled
317 * @param DMAx DMA instance
318 * @retval State of bit (1 or 0).
319 */
FL_DMA_IsEnabled(DMA_Type * DMAx)320 __STATIC_INLINE uint32_t FL_DMA_IsEnabled(DMA_Type *DMAx)
321 {
322 return (uint32_t)(READ_BIT(DMAx->GCR, DMA_GCR_EN_Msk) == DMA_GCR_EN_Msk);
323 }
324
325 /**
326 * @brief DMA disable
327 * @rmtoll GCR EN FL_DMA_Disable
328 * @param DMAx DMA instance
329 * @retval None
330 */
FL_DMA_Disable(DMA_Type * DMAx)331 __STATIC_INLINE void FL_DMA_Disable(DMA_Type *DMAx)
332 {
333 CLEAR_BIT(DMAx->GCR, DMA_GCR_EN_Msk);
334 }
335
336 /**
337 * @brief Set channelx transmission length
338 * @rmtoll CHCR TSIZE FL_DMA_WriteTransmissionSize
339 * @param DMAx DMA instance
340 * @param size
341 * @param channel This parameter can be one of the following values:
342 * @arg @ref FL_DMA_CHANNEL_0
343 * @arg @ref FL_DMA_CHANNEL_1
344 * @arg @ref FL_DMA_CHANNEL_2
345 * @arg @ref FL_DMA_CHANNEL_3
346 * @arg @ref FL_DMA_CHANNEL_4
347 * @arg @ref FL_DMA_CHANNEL_5
348 * @arg @ref FL_DMA_CHANNEL_6
349 * @arg @ref FL_DMA_CHANNEL_7
350 * @retval None
351 */
FL_DMA_WriteTransmissionSize(DMA_Type * DMAx,uint32_t size,uint32_t channel)352 __STATIC_INLINE void FL_DMA_WriteTransmissionSize(DMA_Type *DMAx, uint32_t size, uint32_t channel)
353 {
354 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
355 if(channel <= FL_DMA_CHANNEL_6)
356 {
357 MODIFY_REG(Temp->Channel[channel].CHCR, (0xffffU << 16U), (size << 16U));
358 }
359 else
360 {
361 MODIFY_REG(Temp->CH7CR, (0xffffU << 16U), (size << 16U));
362 }
363 }
364
365 /**
366 * @brief Get channelx transmission length
367 * @rmtoll CHCR TSIZE FL_DMA_ReadTransmissionSize
368 * @param DMAx DMA instance
369 * @param channel This parameter can be one of the following values:
370 * @arg @ref FL_DMA_CHANNEL_0
371 * @arg @ref FL_DMA_CHANNEL_1
372 * @arg @ref FL_DMA_CHANNEL_2
373 * @arg @ref FL_DMA_CHANNEL_3
374 * @arg @ref FL_DMA_CHANNEL_4
375 * @arg @ref FL_DMA_CHANNEL_5
376 * @arg @ref FL_DMA_CHANNEL_6
377 * @arg @ref FL_DMA_CHANNEL_7
378 * @retval
379 */
FL_DMA_ReadTransmissionSize(DMA_Type * DMAx,uint32_t channel)380 __STATIC_INLINE uint32_t FL_DMA_ReadTransmissionSize(DMA_Type *DMAx, uint32_t channel)
381 {
382 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
383 if(channel <= FL_DMA_CHANNEL_6)
384 {
385 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, 0xffffU) >> 16U);
386 }
387 else
388 {
389 return (uint32_t)(READ_BIT(Temp->CH7CR, 0xffffU) >> 16U);
390 }
391 }
392
393 /**
394 * @brief Set channelx priority
395 * @rmtoll CHCR PRI FL_DMA_SetPriority
396 * @param DMAx DMA instance
397 * @param priority This parameter can be one of the following values:
398 * @arg @ref FL_DMA_PRIORITY_LOW
399 * @arg @ref FL_DMA_PRIORITY_MEDIUM
400 * @arg @ref FL_DMA_PRIORITY_HIGH
401 * @arg @ref FL_DMA_PRIORITY_VERYHIGH
402 * @param channel This parameter can be one of the following values:
403 * @arg @ref FL_DMA_CHANNEL_0
404 * @arg @ref FL_DMA_CHANNEL_1
405 * @arg @ref FL_DMA_CHANNEL_2
406 * @arg @ref FL_DMA_CHANNEL_3
407 * @arg @ref FL_DMA_CHANNEL_4
408 * @arg @ref FL_DMA_CHANNEL_5
409 * @arg @ref FL_DMA_CHANNEL_6
410 * @arg @ref FL_DMA_CHANNEL_7
411 * @retval None
412 */
FL_DMA_SetPriority(DMA_Type * DMAx,uint32_t priority,uint32_t channel)413 __STATIC_INLINE void FL_DMA_SetPriority(DMA_Type *DMAx, uint32_t priority, uint32_t channel)
414 {
415 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
416 if(channel <= FL_DMA_CHANNEL_6)
417 {
418 MODIFY_REG(Temp->Channel[channel].CHCR, DMA_CHCR_PRI_Msk, priority);
419 }
420 else
421 {
422 MODIFY_REG(Temp->CH7CR, DMA_CHCR_PRI_Msk, priority);
423 }
424 }
425
426 /**
427 * @brief Get channelx priority
428 * @rmtoll CHCR PRI FL_DMA_GetPriority
429 * @param DMAx DMA instance
430 * @param channel This parameter can be one of the following values:
431 * @arg @ref FL_DMA_CHANNEL_0
432 * @arg @ref FL_DMA_CHANNEL_1
433 * @arg @ref FL_DMA_CHANNEL_2
434 * @arg @ref FL_DMA_CHANNEL_3
435 * @arg @ref FL_DMA_CHANNEL_4
436 * @arg @ref FL_DMA_CHANNEL_5
437 * @arg @ref FL_DMA_CHANNEL_6
438 * @arg @ref FL_DMA_CHANNEL_7
439 * @retval Returned value can be one of the following values:
440 * @arg @ref FL_DMA_PRIORITY_LOW
441 * @arg @ref FL_DMA_PRIORITY_MEDIUM
442 * @arg @ref FL_DMA_PRIORITY_HIGH
443 * @arg @ref FL_DMA_PRIORITY_VERYHIGH
444 */
FL_DMA_GetPriority(DMA_Type * DMAx,uint32_t channel)445 __STATIC_INLINE uint32_t FL_DMA_GetPriority(DMA_Type *DMAx, uint32_t channel)
446 {
447 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
448 if(channel <= FL_DMA_CHANNEL_6)
449 {
450 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_PRI_Msk));
451 }
452 else
453 {
454 return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CHCR_PRI_Msk));
455 }
456 }
457
458 /**
459 * @brief Set channelx RAM address incremental
460 * @rmtoll CHCR INC FL_DMA_SetMemoryIncrementMode
461 * @param DMAx DMA instance
462 * @param mode This parameter can be one of the following values:
463 * @arg @ref FL_DMA_MEMORY_INC_MODE_INCREASE
464 * @arg @ref FL_DMA_MEMORY_INC_MODE_DECREASE
465 * @param channel This parameter can be one of the following values:
466 * @arg @ref FL_DMA_CHANNEL_0
467 * @arg @ref FL_DMA_CHANNEL_1
468 * @arg @ref FL_DMA_CHANNEL_2
469 * @arg @ref FL_DMA_CHANNEL_3
470 * @arg @ref FL_DMA_CHANNEL_4
471 * @arg @ref FL_DMA_CHANNEL_5
472 * @arg @ref FL_DMA_CHANNEL_6
473 * @arg @ref FL_DMA_CHANNEL_7
474 * @retval None
475 */
FL_DMA_SetMemoryIncrementMode(DMA_Type * DMAx,uint32_t mode,uint32_t channel)476 __STATIC_INLINE void FL_DMA_SetMemoryIncrementMode(DMA_Type *DMAx, uint32_t mode, uint32_t channel)
477 {
478 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
479 if(channel <= FL_DMA_CHANNEL_6)
480 {
481 MODIFY_REG(Temp->Channel[channel].CHCR, DMA_CHCR_INC_Msk, mode);
482 }
483 else
484 {
485 MODIFY_REG(Temp->CH7CR, DMA_CH7CR_MEMORY_INC_Msk, mode);
486 }
487 }
488
489 /**
490 * @brief Get channelx RAM address incremental status
491 * @rmtoll CHCR INC FL_DMA_GetMemoryIncrementMode
492 * @param DMAx DMA instance
493 * @param channel This parameter can be one of the following values:
494 * @arg @ref FL_DMA_CHANNEL_0
495 * @arg @ref FL_DMA_CHANNEL_1
496 * @arg @ref FL_DMA_CHANNEL_2
497 * @arg @ref FL_DMA_CHANNEL_3
498 * @arg @ref FL_DMA_CHANNEL_4
499 * @arg @ref FL_DMA_CHANNEL_5
500 * @arg @ref FL_DMA_CHANNEL_6
501 * @arg @ref FL_DMA_CHANNEL_7
502 * @retval Returned value can be one of the following values:
503 * @arg @ref FL_DMA_MEMORY_INC_MODE_INCREASE
504 * @arg @ref FL_DMA_MEMORY_INC_MODE_DECREASE
505 */
FL_DMA_GetMemoryIncrementMode(DMA_Type * DMAx,uint32_t channel)506 __STATIC_INLINE uint32_t FL_DMA_GetMemoryIncrementMode(DMA_Type *DMAx, uint32_t channel)
507 {
508 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
509 if(channel <= FL_DMA_CHANNEL_6)
510 {
511 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_INC_Msk));
512 }
513 else
514 {
515 return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CH7CR_MEMORY_INC_Msk));
516 }
517 }
518
519 /**
520 * @brief Set channel7 FLASH address incremental
521 * @rmtoll CH7CR FLASH_INC FL_DMA_SetFlashIncrementMode
522 * @param DMAx DMA instance
523 * @param mode This parameter can be one of the following values:
524 * @arg @ref FL_DMA_FLASH_INC_MODE_INCREASE
525 * @arg @ref FL_DMA_FLASH_INC_MODE_DECREASE
526 * @retval None
527 */
FL_DMA_SetFlashIncrementMode(DMA_Type * DMAx,uint32_t mode)528 __STATIC_INLINE void FL_DMA_SetFlashIncrementMode(DMA_Type *DMAx, uint32_t mode)
529 {
530 MODIFY_REG(DMAx->CH7CR, DMA_CH7CR_FLASH_INC_Msk, mode);
531 }
532
533 /**
534 * @brief Get channel7 FLASH address incremental status
535 * @rmtoll CH7CR FLASH_INC FL_DMA_GetFlashIncrementMode
536 * @param DMAx DMA instance
537 * @retval Returned value can be one of the following values:
538 * @arg @ref FL_DMA_FLASH_INC_MODE_INCREASE
539 * @arg @ref FL_DMA_FLASH_INC_MODE_DECREASE
540 */
FL_DMA_GetFlashIncrementMode(DMA_Type * DMAx)541 __STATIC_INLINE uint32_t FL_DMA_GetFlashIncrementMode(DMA_Type *DMAx)
542 {
543 return (uint32_t)(READ_BIT(DMAx->CH7CR, DMA_CH7CR_FLASH_INC_Msk));
544 }
545
546 /**
547 * @brief Channelx request source select
548 * @rmtoll CHCR SSEL FL_DMA_SetPeripheralMap
549 * @param DMAx DMA instance
550 * @param peripheral This parameter can be one of the following values:
551 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION1
552 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION2
553 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION3
554 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION4
555 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION5
556 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION6
557 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION7
558 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION8
559 * @param channel This parameter can be one of the following values:
560 * @arg @ref FL_DMA_CHANNEL_0
561 * @arg @ref FL_DMA_CHANNEL_1
562 * @arg @ref FL_DMA_CHANNEL_2
563 * @arg @ref FL_DMA_CHANNEL_3
564 * @arg @ref FL_DMA_CHANNEL_4
565 * @arg @ref FL_DMA_CHANNEL_5
566 * @arg @ref FL_DMA_CHANNEL_6
567 * @arg @ref FL_DMA_CHANNEL_7
568 * @retval None
569 */
FL_DMA_SetPeripheralMap(DMA_Type * DMAx,uint32_t peripheral,uint32_t channel)570 __STATIC_INLINE void FL_DMA_SetPeripheralMap(DMA_Type *DMAx, uint32_t peripheral, uint32_t channel)
571 {
572 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
573 if(channel <= FL_DMA_CHANNEL_6)
574 {
575 MODIFY_REG(Temp->Channel[channel].CHCR, DMA_CHCR_SSEL_Msk, peripheral);
576 }
577 }
578
579 /**
580 * @brief Get Channelx request source select status
581 * @rmtoll CHCR SSEL FL_DMA_GetPeripheralMap
582 * @param DMAx DMA instance
583 * @param channel This parameter can be one of the following values:
584 * @arg @ref FL_DMA_CHANNEL_0
585 * @arg @ref FL_DMA_CHANNEL_1
586 * @arg @ref FL_DMA_CHANNEL_2
587 * @arg @ref FL_DMA_CHANNEL_3
588 * @arg @ref FL_DMA_CHANNEL_4
589 * @arg @ref FL_DMA_CHANNEL_5
590 * @arg @ref FL_DMA_CHANNEL_6
591 * @arg @ref FL_DMA_CHANNEL_7
592 * @retval Returned value can be one of the following values:
593 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION1
594 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION2
595 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION3
596 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION4
597 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION5
598 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION6
599 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION7
600 * @arg @ref FL_DMA_PERIPHERAL_FUNCTION8
601 */
FL_DMA_GetPeripheralMap(DMA_Type * DMAx,uint32_t channel)602 __STATIC_INLINE uint32_t FL_DMA_GetPeripheralMap(DMA_Type *DMAx, uint32_t channel)
603 {
604 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
605 if(channel <= FL_DMA_CHANNEL_6)
606 {
607 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_SSEL_Msk));
608 }
609 return 0;
610 }
611
612 /**
613 * @brief Set channelx transmit direction
614 * @rmtoll CHCR DIR FL_DMA_SetTransmissionDirection
615 * @param DMAx DMA instance
616 * @param direction This parameter can be one of the following values:
617 * @arg @ref FL_DMA_DIR_PERIPHERAL_TO_RAM
618 * @arg @ref FL_DMA_DIR_RAM_TO_PERIPHERAL
619 * @param channel This parameter can be one of the following values:
620 * @arg @ref FL_DMA_CHANNEL_0
621 * @arg @ref FL_DMA_CHANNEL_1
622 * @arg @ref FL_DMA_CHANNEL_2
623 * @arg @ref FL_DMA_CHANNEL_3
624 * @arg @ref FL_DMA_CHANNEL_4
625 * @arg @ref FL_DMA_CHANNEL_5
626 * @arg @ref FL_DMA_CHANNEL_6
627 * @arg @ref FL_DMA_CHANNEL_7
628 * @retval None
629 */
FL_DMA_SetTransmissionDirection(DMA_Type * DMAx,uint32_t direction,uint32_t channel)630 __STATIC_INLINE void FL_DMA_SetTransmissionDirection(DMA_Type *DMAx, uint32_t direction, uint32_t channel)
631 {
632 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
633 if(channel <= FL_DMA_CHANNEL_6)
634 {
635 MODIFY_REG(Temp->Channel[channel].CHCR, DMA_CHCR_DIR_Msk, direction);
636 }
637 else
638 {
639 MODIFY_REG(Temp->CH7CR, DMA_CH7CR_DIR_Msk, direction);
640 }
641 }
642
643 /**
644 * @brief Get channelx transmit direction
645 * @rmtoll CHCR DIR FL_DMA_GetTransmissionDirection
646 * @param DMAx DMA instance
647 * @param channel This parameter can be one of the following values:
648 * @arg @ref FL_DMA_CHANNEL_0
649 * @arg @ref FL_DMA_CHANNEL_1
650 * @arg @ref FL_DMA_CHANNEL_2
651 * @arg @ref FL_DMA_CHANNEL_3
652 * @arg @ref FL_DMA_CHANNEL_4
653 * @arg @ref FL_DMA_CHANNEL_5
654 * @arg @ref FL_DMA_CHANNEL_6
655 * @arg @ref FL_DMA_CHANNEL_7
656 * @retval Returned value can be one of the following values:
657 * @arg @ref FL_DMA_DIR_PERIPHERAL_TO_RAM
658 * @arg @ref FL_DMA_DIR_RAM_TO_PERIPHERAL
659 */
FL_DMA_GetTransmissionDirection(DMA_Type * DMAx,uint32_t channel)660 __STATIC_INLINE uint32_t FL_DMA_GetTransmissionDirection(DMA_Type *DMAx, uint32_t channel)
661 {
662 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
663 if(channel <= FL_DMA_CHANNEL_6)
664 {
665 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_DIR_Msk));
666 }
667 else
668 {
669 return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CH7CR_DIR_Msk));
670 }
671 }
672
673 /**
674 * @brief Set transmit bandwidth
675 * @rmtoll CHCR BDW FL_DMA_SetBandwidth
676 * @param DMAx DMA instance
677 * @param bandwidth This parameter can be one of the following values:
678 * @arg @ref FL_DMA_BANDWIDTH_8B
679 * @arg @ref FL_DMA_BANDWIDTH_16B
680 * @arg @ref FL_DMA_BANDWIDTH_32B
681 * @param channel This parameter can be one of the following values:
682 * @arg @ref FL_DMA_CHANNEL_0
683 * @arg @ref FL_DMA_CHANNEL_1
684 * @arg @ref FL_DMA_CHANNEL_2
685 * @arg @ref FL_DMA_CHANNEL_3
686 * @arg @ref FL_DMA_CHANNEL_4
687 * @arg @ref FL_DMA_CHANNEL_5
688 * @arg @ref FL_DMA_CHANNEL_6
689 * @arg @ref FL_DMA_CHANNEL_7
690 * @retval None
691 */
FL_DMA_SetBandwidth(DMA_Type * DMAx,uint32_t bandwidth,uint32_t channel)692 __STATIC_INLINE void FL_DMA_SetBandwidth(DMA_Type *DMAx, uint32_t bandwidth, uint32_t channel)
693 {
694 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
695 if(channel <= FL_DMA_CHANNEL_6)
696 {
697 MODIFY_REG(Temp->Channel[channel].CHCR, DMA_CHCR_BDW_Msk, bandwidth);
698 }
699 }
700
701 /**
702 * @brief Get transmit bandwidth
703 * @rmtoll CHCR BDW FL_DMA_GetBandwidth
704 * @param DMAx DMA instance
705 * @param channel This parameter can be one of the following values:
706 * @arg @ref FL_DMA_CHANNEL_0
707 * @arg @ref FL_DMA_CHANNEL_1
708 * @arg @ref FL_DMA_CHANNEL_2
709 * @arg @ref FL_DMA_CHANNEL_3
710 * @arg @ref FL_DMA_CHANNEL_4
711 * @arg @ref FL_DMA_CHANNEL_5
712 * @arg @ref FL_DMA_CHANNEL_6
713 * @arg @ref FL_DMA_CHANNEL_7
714 * @retval Returned value can be one of the following values:
715 * @arg @ref FL_DMA_BANDWIDTH_8B
716 * @arg @ref FL_DMA_BANDWIDTH_16B
717 * @arg @ref FL_DMA_BANDWIDTH_32B
718 */
FL_DMA_GetBandwidth(DMA_Type * DMAx,uint32_t channel)719 __STATIC_INLINE uint32_t FL_DMA_GetBandwidth(DMA_Type *DMAx, uint32_t channel)
720 {
721 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
722 if(channel <= FL_DMA_CHANNEL_6)
723 {
724 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_BDW_Msk));
725 }
726 return 0;
727 }
728
729 /**
730 * @brief Circular mode enable
731 * @rmtoll CHCR CIRC FL_DMA_EnableCircularMode
732 * @param DMAx DMA instance
733 * @param channel This parameter can be one of the following values:
734 * @arg @ref FL_DMA_CHANNEL_0
735 * @arg @ref FL_DMA_CHANNEL_1
736 * @arg @ref FL_DMA_CHANNEL_2
737 * @arg @ref FL_DMA_CHANNEL_3
738 * @arg @ref FL_DMA_CHANNEL_4
739 * @arg @ref FL_DMA_CHANNEL_5
740 * @arg @ref FL_DMA_CHANNEL_6
741 * @arg @ref FL_DMA_CHANNEL_7
742 * @retval None
743 */
FL_DMA_EnableCircularMode(DMA_Type * DMAx,uint32_t channel)744 __STATIC_INLINE void FL_DMA_EnableCircularMode(DMA_Type *DMAx, uint32_t channel)
745 {
746 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
747 if(channel <= FL_DMA_CHANNEL_6)
748 {
749 SET_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_CIRC_Msk);
750 }
751 else
752 {
753 SET_BIT(Temp->CH7CR, DMA_CHCR_CIRC_Msk);
754 }
755 }
756
757 /**
758 * @brief Get circular mode enable status
759 * @rmtoll CHCR CIRC FL_DMA_IsEnabledCircularMode
760 * @param DMAx DMA instance
761 * @param channel This parameter can be one of the following values:
762 * @arg @ref FL_DMA_CHANNEL_0
763 * @arg @ref FL_DMA_CHANNEL_1
764 * @arg @ref FL_DMA_CHANNEL_2
765 * @arg @ref FL_DMA_CHANNEL_3
766 * @arg @ref FL_DMA_CHANNEL_4
767 * @arg @ref FL_DMA_CHANNEL_5
768 * @arg @ref FL_DMA_CHANNEL_6
769 * @arg @ref FL_DMA_CHANNEL_7
770 * @retval State of bit (1 or 0).
771 */
FL_DMA_IsEnabledCircularMode(DMA_Type * DMAx,uint32_t channel)772 __STATIC_INLINE uint32_t FL_DMA_IsEnabledCircularMode(DMA_Type *DMAx, uint32_t channel)
773 {
774 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
775 if(channel <= FL_DMA_CHANNEL_6)
776 {
777 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_CIRC_Msk) == DMA_CHCR_CIRC_Msk);
778 }
779 else
780 {
781 return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CHCR_CIRC_Msk) == DMA_CHCR_CIRC_Msk);
782 }
783 }
784
785 /**
786 * @brief Circular mode disable
787 * @rmtoll CHCR CIRC FL_DMA_DisableCircularMode
788 * @param DMAx DMA instance
789 * @param channel This parameter can be one of the following values:
790 * @arg @ref FL_DMA_CHANNEL_0
791 * @arg @ref FL_DMA_CHANNEL_1
792 * @arg @ref FL_DMA_CHANNEL_2
793 * @arg @ref FL_DMA_CHANNEL_3
794 * @arg @ref FL_DMA_CHANNEL_4
795 * @arg @ref FL_DMA_CHANNEL_5
796 * @arg @ref FL_DMA_CHANNEL_6
797 * @arg @ref FL_DMA_CHANNEL_7
798 * @retval None
799 */
FL_DMA_DisableCircularMode(DMA_Type * DMAx,uint32_t channel)800 __STATIC_INLINE void FL_DMA_DisableCircularMode(DMA_Type *DMAx, uint32_t channel)
801 {
802 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
803 if(channel <= FL_DMA_CHANNEL_6)
804 {
805 CLEAR_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_CIRC_Msk);
806 }
807 else
808 {
809 CLEAR_BIT(Temp->CH7CR, DMA_CHCR_CIRC_Msk);
810 }
811 }
812
813 /**
814 * @brief channelx transmit finished interrupt enable
815 * @rmtoll CHCR FTIE FL_DMA_EnableIT_TransferComplete
816 * @param DMAx DMA instance
817 * @param channel This parameter can be one of the following values:
818 * @arg @ref FL_DMA_CHANNEL_0
819 * @arg @ref FL_DMA_CHANNEL_1
820 * @arg @ref FL_DMA_CHANNEL_2
821 * @arg @ref FL_DMA_CHANNEL_3
822 * @arg @ref FL_DMA_CHANNEL_4
823 * @arg @ref FL_DMA_CHANNEL_5
824 * @arg @ref FL_DMA_CHANNEL_6
825 * @arg @ref FL_DMA_CHANNEL_7
826 * @retval None
827 */
FL_DMA_EnableIT_TransferComplete(DMA_Type * DMAx,uint32_t channel)828 __STATIC_INLINE void FL_DMA_EnableIT_TransferComplete(DMA_Type *DMAx, uint32_t channel)
829 {
830 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
831 if(channel <= FL_DMA_CHANNEL_6)
832 {
833 SET_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_FTIE_Msk);
834 }
835 else
836 {
837 SET_BIT(Temp->CH7CR, DMA_CHCR_FTIE_Msk);
838 }
839 }
840
841 /**
842 * @brief Get channelx transmit finished interrupt enable status
843 * @rmtoll CHCR FTIE FL_DMA_IsEnabledIT_TransferComplete
844 * @param DMAx DMA instance
845 * @param channel This parameter can be one of the following values:
846 * @arg @ref FL_DMA_CHANNEL_0
847 * @arg @ref FL_DMA_CHANNEL_1
848 * @arg @ref FL_DMA_CHANNEL_2
849 * @arg @ref FL_DMA_CHANNEL_3
850 * @arg @ref FL_DMA_CHANNEL_4
851 * @arg @ref FL_DMA_CHANNEL_5
852 * @arg @ref FL_DMA_CHANNEL_6
853 * @arg @ref FL_DMA_CHANNEL_7
854 * @retval State of bit (1 or 0).
855 */
FL_DMA_IsEnabledIT_TransferComplete(DMA_Type * DMAx,uint32_t channel)856 __STATIC_INLINE uint32_t FL_DMA_IsEnabledIT_TransferComplete(DMA_Type *DMAx, uint32_t channel)
857 {
858 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
859 if(channel <= FL_DMA_CHANNEL_6)
860 {
861 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_FTIE_Msk) == DMA_CHCR_FTIE_Msk);
862 }
863 else
864 {
865 return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CHCR_FTIE_Msk) == DMA_CHCR_FTIE_Msk);
866 }
867 }
868
869 /**
870 * @brief channelx transmit finished interrupt disable
871 * @rmtoll CHCR FTIE FL_DMA_DisableIT_TransferComplete
872 * @param DMAx DMA instance
873 * @param channel This parameter can be one of the following values:
874 * @arg @ref FL_DMA_CHANNEL_0
875 * @arg @ref FL_DMA_CHANNEL_1
876 * @arg @ref FL_DMA_CHANNEL_2
877 * @arg @ref FL_DMA_CHANNEL_3
878 * @arg @ref FL_DMA_CHANNEL_4
879 * @arg @ref FL_DMA_CHANNEL_5
880 * @arg @ref FL_DMA_CHANNEL_6
881 * @arg @ref FL_DMA_CHANNEL_7
882 * @retval None
883 */
FL_DMA_DisableIT_TransferComplete(DMA_Type * DMAx,uint32_t channel)884 __STATIC_INLINE void FL_DMA_DisableIT_TransferComplete(DMA_Type *DMAx, uint32_t channel)
885 {
886 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
887 if(channel <= FL_DMA_CHANNEL_6)
888 {
889 CLEAR_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_FTIE_Msk);
890 }
891 else
892 {
893 CLEAR_BIT(Temp->CH7CR, DMA_CHCR_FTIE_Msk);
894 }
895 }
896
897 /**
898 * @brief Channelx Half-transfer interrupt enable
899 * @rmtoll CHCR HTIE FL_DMA_EnableIT_TransferHalfComplete
900 * @param DMAx DMA instance
901 * @param channel This parameter can be one of the following values:
902 * @arg @ref FL_DMA_CHANNEL_0
903 * @arg @ref FL_DMA_CHANNEL_1
904 * @arg @ref FL_DMA_CHANNEL_2
905 * @arg @ref FL_DMA_CHANNEL_3
906 * @arg @ref FL_DMA_CHANNEL_4
907 * @arg @ref FL_DMA_CHANNEL_5
908 * @arg @ref FL_DMA_CHANNEL_6
909 * @arg @ref FL_DMA_CHANNEL_7
910 * @retval None
911 */
FL_DMA_EnableIT_TransferHalfComplete(DMA_Type * DMAx,uint32_t channel)912 __STATIC_INLINE void FL_DMA_EnableIT_TransferHalfComplete(DMA_Type *DMAx, uint32_t channel)
913 {
914 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
915 if(channel <= FL_DMA_CHANNEL_6)
916 {
917 SET_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_HTIE_Msk);
918 }
919 else
920 {
921 SET_BIT(Temp->CH7CR, DMA_CHCR_HTIE_Msk);
922 }
923 }
924
925 /**
926 * @brief Get Channelx Half-transfer interrupt enable status
927 * @rmtoll CHCR HTIE FL_DMA_IsEnabledIT_TransferHalfComplete
928 * @param DMAx DMA instance
929 * @param channel This parameter can be one of the following values:
930 * @arg @ref FL_DMA_CHANNEL_0
931 * @arg @ref FL_DMA_CHANNEL_1
932 * @arg @ref FL_DMA_CHANNEL_2
933 * @arg @ref FL_DMA_CHANNEL_3
934 * @arg @ref FL_DMA_CHANNEL_4
935 * @arg @ref FL_DMA_CHANNEL_5
936 * @arg @ref FL_DMA_CHANNEL_6
937 * @arg @ref FL_DMA_CHANNEL_7
938 * @retval State of bit (1 or 0).
939 */
FL_DMA_IsEnabledIT_TransferHalfComplete(DMA_Type * DMAx,uint32_t channel)940 __STATIC_INLINE uint32_t FL_DMA_IsEnabledIT_TransferHalfComplete(DMA_Type *DMAx, uint32_t channel)
941 {
942 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
943 if(channel <= FL_DMA_CHANNEL_6)
944 {
945 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_HTIE_Msk) == DMA_CHCR_HTIE_Msk);
946 }
947 else
948 {
949 return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CHCR_HTIE_Msk) == DMA_CHCR_HTIE_Msk);
950 }
951 }
952
953 /**
954 * @brief Channelx Half-transfer interrupt disable
955 * @rmtoll CHCR HTIE FL_DMA_DisableIT_TransferHalfComplete
956 * @param DMAx DMA instance
957 * @param channel This parameter can be one of the following values:
958 * @arg @ref FL_DMA_CHANNEL_0
959 * @arg @ref FL_DMA_CHANNEL_1
960 * @arg @ref FL_DMA_CHANNEL_2
961 * @arg @ref FL_DMA_CHANNEL_3
962 * @arg @ref FL_DMA_CHANNEL_4
963 * @arg @ref FL_DMA_CHANNEL_5
964 * @arg @ref FL_DMA_CHANNEL_6
965 * @arg @ref FL_DMA_CHANNEL_7
966 * @retval None
967 */
FL_DMA_DisableIT_TransferHalfComplete(DMA_Type * DMAx,uint32_t channel)968 __STATIC_INLINE void FL_DMA_DisableIT_TransferHalfComplete(DMA_Type *DMAx, uint32_t channel)
969 {
970 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
971 if(channel <= FL_DMA_CHANNEL_6)
972 {
973 CLEAR_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_HTIE_Msk);
974 }
975 else
976 {
977 CLEAR_BIT(Temp->CH7CR, DMA_CHCR_HTIE_Msk);
978 }
979 }
980
981 /**
982 * @brief Channelx enable
983 * @rmtoll CHCR EN FL_DMA_EnableChannel
984 * @param DMAx DMA instance
985 * @param channel This parameter can be one of the following values:
986 * @arg @ref FL_DMA_CHANNEL_0
987 * @arg @ref FL_DMA_CHANNEL_1
988 * @arg @ref FL_DMA_CHANNEL_2
989 * @arg @ref FL_DMA_CHANNEL_3
990 * @arg @ref FL_DMA_CHANNEL_4
991 * @arg @ref FL_DMA_CHANNEL_5
992 * @arg @ref FL_DMA_CHANNEL_6
993 * @arg @ref FL_DMA_CHANNEL_7
994 * @retval None
995 */
FL_DMA_EnableChannel(DMA_Type * DMAx,uint32_t channel)996 __STATIC_INLINE void FL_DMA_EnableChannel(DMA_Type *DMAx, uint32_t channel)
997 {
998 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
999 if(channel <= FL_DMA_CHANNEL_6)
1000 {
1001 SET_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_EN_Msk);
1002 }
1003 else
1004 {
1005 SET_BIT(Temp->CH7CR, DMA_CHCR_EN_Msk);
1006 }
1007 }
1008
1009 /**
1010 * @brief Get channelx enable status
1011 * @rmtoll CHCR EN FL_DMA_IsEnabledChannel
1012 * @param DMAx DMA instance
1013 * @param channel This parameter can be one of the following values:
1014 * @arg @ref FL_DMA_CHANNEL_0
1015 * @arg @ref FL_DMA_CHANNEL_1
1016 * @arg @ref FL_DMA_CHANNEL_2
1017 * @arg @ref FL_DMA_CHANNEL_3
1018 * @arg @ref FL_DMA_CHANNEL_4
1019 * @arg @ref FL_DMA_CHANNEL_5
1020 * @arg @ref FL_DMA_CHANNEL_6
1021 * @arg @ref FL_DMA_CHANNEL_7
1022 * @retval State of bit (1 or 0).
1023 */
FL_DMA_IsEnabledChannel(DMA_Type * DMAx,uint32_t channel)1024 __STATIC_INLINE uint32_t FL_DMA_IsEnabledChannel(DMA_Type *DMAx, uint32_t channel)
1025 {
1026 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
1027 if(channel <= FL_DMA_CHANNEL_6)
1028 {
1029 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_EN_Msk) == DMA_CHCR_EN_Msk);
1030 }
1031 else
1032 {
1033 return (uint32_t)(READ_BIT(Temp->CH7CR, DMA_CHCR_EN_Msk) == DMA_CHCR_EN_Msk);
1034 }
1035 }
1036
1037 /**
1038 * @brief Channelx disable
1039 * @rmtoll CHCR EN FL_DMA_DisableChannel
1040 * @param DMAx DMA instance
1041 * @param channel This parameter can be one of the following values:
1042 * @arg @ref FL_DMA_CHANNEL_0
1043 * @arg @ref FL_DMA_CHANNEL_1
1044 * @arg @ref FL_DMA_CHANNEL_2
1045 * @arg @ref FL_DMA_CHANNEL_3
1046 * @arg @ref FL_DMA_CHANNEL_4
1047 * @arg @ref FL_DMA_CHANNEL_5
1048 * @arg @ref FL_DMA_CHANNEL_6
1049 * @arg @ref FL_DMA_CHANNEL_7
1050 * @retval None
1051 */
FL_DMA_DisableChannel(DMA_Type * DMAx,uint32_t channel)1052 __STATIC_INLINE void FL_DMA_DisableChannel(DMA_Type *DMAx, uint32_t channel)
1053 {
1054 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
1055 if(channel <= FL_DMA_CHANNEL_6)
1056 {
1057 CLEAR_BIT(Temp->Channel[channel].CHCR, DMA_CHCR_EN_Msk);
1058 }
1059 else
1060 {
1061 CLEAR_BIT(Temp->CH7CR, DMA_CHCR_EN_Msk);
1062 }
1063 }
1064
1065 /**
1066 * @brief Set channelx memory pointer address
1067 * @rmtoll MEMAD FL_DMA_WriteMemoryAddress
1068 * @param DMAx DMA instance
1069 * @param data
1070 * @param channel This parameter can be one of the following values:
1071 * @arg @ref FL_DMA_CHANNEL_0
1072 * @arg @ref FL_DMA_CHANNEL_1
1073 * @arg @ref FL_DMA_CHANNEL_2
1074 * @arg @ref FL_DMA_CHANNEL_3
1075 * @arg @ref FL_DMA_CHANNEL_4
1076 * @arg @ref FL_DMA_CHANNEL_5
1077 * @arg @ref FL_DMA_CHANNEL_6
1078 * @arg @ref FL_DMA_CHANNEL_7
1079 * @retval None
1080 */
FL_DMA_WriteMemoryAddress(DMA_Type * DMAx,uint32_t data,uint32_t channel)1081 __STATIC_INLINE void FL_DMA_WriteMemoryAddress(DMA_Type *DMAx, uint32_t data, uint32_t channel)
1082 {
1083 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
1084 if(channel <= FL_DMA_CHANNEL_6)
1085 {
1086 MODIFY_REG(Temp->Channel[channel].CHMAD, (0xffffffffU), (data));
1087 }
1088 else
1089 {
1090 MODIFY_REG(Temp->CH7MAD, (0xffffffffU), (data));
1091 }
1092 }
1093
1094 /**
1095 * @brief Get channelx memory pointer address
1096 * @rmtoll MEMAD FL_DMA_ReadMemoryAddress
1097 * @param DMAx DMA instance
1098 * @param channel This parameter can be one of the following values:
1099 * @arg @ref FL_DMA_CHANNEL_0
1100 * @arg @ref FL_DMA_CHANNEL_1
1101 * @arg @ref FL_DMA_CHANNEL_2
1102 * @arg @ref FL_DMA_CHANNEL_3
1103 * @arg @ref FL_DMA_CHANNEL_4
1104 * @arg @ref FL_DMA_CHANNEL_5
1105 * @arg @ref FL_DMA_CHANNEL_6
1106 * @arg @ref FL_DMA_CHANNEL_7
1107 * @retval
1108 */
FL_DMA_ReadMemoryAddress(DMA_Type * DMAx,uint32_t channel)1109 __STATIC_INLINE uint32_t FL_DMA_ReadMemoryAddress(DMA_Type *DMAx, uint32_t channel)
1110 {
1111 DMA_ADDR *Temp = (DMA_ADDR *)DMAx;
1112 if(channel <= FL_DMA_CHANNEL_6)
1113 {
1114 return (uint32_t)(READ_BIT(Temp->Channel[channel].CHMAD, (0xffffffffU)));
1115 }
1116 else
1117 {
1118 return (uint32_t)(READ_BIT(Temp->CH7MAD, (0xffffffffU)));
1119 }
1120 }
1121
1122 /**
1123 * @brief Set channel7 flash pointer address
1124 * @rmtoll CH7FLSAD FL_DMA_WriteFlashAddress
1125 * @param DMAx DMA instance
1126 * @param data
1127 * @retval None
1128 */
FL_DMA_WriteFlashAddress(DMA_Type * DMAx,uint32_t data)1129 __STATIC_INLINE void FL_DMA_WriteFlashAddress(DMA_Type *DMAx, uint32_t data)
1130 {
1131 MODIFY_REG(DMAx->CH7FLSAD, (0xffffffffU << 0U), (data << 0U));
1132 }
1133
1134 /**
1135 * @brief Get channel7 flash pointer address
1136 * @rmtoll CH7FLSAD FL_DMA_ReadFlashAddress
1137 * @param DMAx DMA instance
1138 * @retval
1139 */
FL_DMA_ReadFlashAddress(DMA_Type * DMAx)1140 __STATIC_INLINE uint32_t FL_DMA_ReadFlashAddress(DMA_Type *DMAx)
1141 {
1142 return (uint32_t)(READ_BIT(DMAx->CH7FLSAD, (0xffffffffU << 0U)) >> 0U);
1143 }
1144
1145 /**
1146 * @brief Get DMA address error flag
1147 * @rmtoll ISR ADDRERR FL_DMA_IsActiveFlag_AddressError
1148 * @param DMAx DMA instance
1149 * @retval State of bit (1 or 0).
1150 */
FL_DMA_IsActiveFlag_AddressError(DMA_Type * DMAx)1151 __STATIC_INLINE uint32_t FL_DMA_IsActiveFlag_AddressError(DMA_Type *DMAx)
1152 {
1153 return (uint32_t)(READ_BIT(DMAx->ISR, DMA_ISR_ADDRERR_Msk) == (DMA_ISR_ADDRERR_Msk));
1154 }
1155
1156 /**
1157 * @brief Clear DMA address error flag
1158 * @rmtoll ISR ADDRERR FL_DMA_ClearFlag_AddressError
1159 * @param DMAx DMA instance
1160 * @retval None
1161 */
FL_DMA_ClearFlag_AddressError(DMA_Type * DMAx)1162 __STATIC_INLINE void FL_DMA_ClearFlag_AddressError(DMA_Type *DMAx)
1163 {
1164 WRITE_REG(DMAx->ISR, DMA_ISR_ADDRERR_Msk);
1165 }
1166
1167 /**
1168 * @brief Get DMA channelx finished-transfer flag
1169 * @rmtoll ISR CHFT FL_DMA_IsActiveFlag_TransferComplete
1170 * @param DMAx DMA instance
1171 * @param channel This parameter can be one of the following values:
1172 * @arg @ref FL_DMA_CHANNEL_0
1173 * @arg @ref FL_DMA_CHANNEL_1
1174 * @arg @ref FL_DMA_CHANNEL_2
1175 * @arg @ref FL_DMA_CHANNEL_3
1176 * @arg @ref FL_DMA_CHANNEL_4
1177 * @arg @ref FL_DMA_CHANNEL_5
1178 * @arg @ref FL_DMA_CHANNEL_6
1179 * @arg @ref FL_DMA_CHANNEL_7
1180 * @retval State of bit (1 or 0).
1181 */
FL_DMA_IsActiveFlag_TransferComplete(DMA_Type * DMAx,uint32_t channel)1182 __STATIC_INLINE uint32_t FL_DMA_IsActiveFlag_TransferComplete(DMA_Type *DMAx, uint32_t channel)
1183 {
1184 return (uint32_t)(READ_BIT(DMAx->ISR, ((0x1U << channel) << DMA_ISR_CHFT_Pos)) == ((0x1U << channel) << DMA_ISR_CHFT_Pos));
1185 }
1186
1187 /**
1188 * @brief Clear DMA channelx finished-transfer flag
1189 * @rmtoll ISR CHFT FL_DMA_ClearFlag_TransferComplete
1190 * @param DMAx DMA instance
1191 * @param channel This parameter can be one of the following values:
1192 * @arg @ref FL_DMA_CHANNEL_0
1193 * @arg @ref FL_DMA_CHANNEL_1
1194 * @arg @ref FL_DMA_CHANNEL_2
1195 * @arg @ref FL_DMA_CHANNEL_3
1196 * @arg @ref FL_DMA_CHANNEL_4
1197 * @arg @ref FL_DMA_CHANNEL_5
1198 * @arg @ref FL_DMA_CHANNEL_6
1199 * @arg @ref FL_DMA_CHANNEL_7
1200 * @retval None
1201 */
FL_DMA_ClearFlag_TransferComplete(DMA_Type * DMAx,uint32_t channel)1202 __STATIC_INLINE void FL_DMA_ClearFlag_TransferComplete(DMA_Type *DMAx, uint32_t channel)
1203 {
1204 WRITE_REG(DMAx->ISR, (DMA_ISR_CHFT_Msk << channel));
1205 }
1206
1207 /**
1208 * @brief Get DMA channel half-transfer flag
1209 * @rmtoll ISR CHHT FL_DMA_IsActiveFlag_TransferHalfComplete
1210 * @param DMAx DMA instance
1211 * @param channel This parameter can be one of the following values:
1212 * @arg @ref FL_DMA_CHANNEL_0
1213 * @arg @ref FL_DMA_CHANNEL_1
1214 * @arg @ref FL_DMA_CHANNEL_2
1215 * @arg @ref FL_DMA_CHANNEL_3
1216 * @arg @ref FL_DMA_CHANNEL_4
1217 * @arg @ref FL_DMA_CHANNEL_5
1218 * @arg @ref FL_DMA_CHANNEL_6
1219 * @arg @ref FL_DMA_CHANNEL_7
1220 * @retval State of bit (1 or 0).
1221 */
FL_DMA_IsActiveFlag_TransferHalfComplete(DMA_Type * DMAx,uint32_t channel)1222 __STATIC_INLINE uint32_t FL_DMA_IsActiveFlag_TransferHalfComplete(DMA_Type *DMAx, uint32_t channel)
1223 {
1224 return (uint32_t)(READ_BIT(DMAx->ISR, ((0x1U << channel) << DMA_ISR_CHHT_Pos)) == ((0x1U << channel) << DMA_ISR_CHHT_Pos));
1225 }
1226
1227 /**
1228 * @brief Clear DMA channel half-transfer flag
1229 * @rmtoll ISR CHHT FL_DMA_ClearFlag_TransferHalfComplete
1230 * @param DMAx DMA instance
1231 * @param channel This parameter can be one of the following values:
1232 * @arg @ref FL_DMA_CHANNEL_0
1233 * @arg @ref FL_DMA_CHANNEL_1
1234 * @arg @ref FL_DMA_CHANNEL_2
1235 * @arg @ref FL_DMA_CHANNEL_3
1236 * @arg @ref FL_DMA_CHANNEL_4
1237 * @arg @ref FL_DMA_CHANNEL_5
1238 * @arg @ref FL_DMA_CHANNEL_6
1239 * @arg @ref FL_DMA_CHANNEL_7
1240 * @retval None
1241 */
FL_DMA_ClearFlag_TransferHalfComplete(DMA_Type * DMAx,uint32_t channel)1242 __STATIC_INLINE void FL_DMA_ClearFlag_TransferHalfComplete(DMA_Type *DMAx, uint32_t channel)
1243 {
1244 WRITE_REG(DMAx->ISR, (DMA_ISR_CHHT_Msk << channel));
1245 }
1246
1247 /**
1248 * @}
1249 */
1250
1251 /** @defgroup DMA_FL_EF_Init Initialization and de-initialization functions
1252 * @{
1253 */
1254 FL_ErrorStatus FL_DMA_DeInit(DMA_Type *DMAx);
1255 FL_ErrorStatus FL_DMA_Init(DMA_Type *DMAx, FL_DMA_InitTypeDef *initStruct, uint32_t channel);
1256 void FL_DMA_StructInit(FL_DMA_InitTypeDef *initStruct);
1257
1258 /**
1259 * @}
1260 */
1261
1262 /** @defgroup DMA_FL_EF_Operation Opeartion functions
1263 * @{
1264 */
1265
1266 FL_ErrorStatus FL_DMA_StartTransmission(DMA_Type *DMAx, FL_DMA_ConfigTypeDef *configStruct, uint32_t channel);
1267
1268 /**
1269 * @}
1270 */
1271
1272 /**
1273 * @}
1274 */
1275
1276 /**
1277 * @}
1278 */
1279
1280 #ifdef __cplusplus
1281 }
1282 #endif
1283
1284 #endif /* __FM33LC0XX_FL_DMA_H*/
1285
1286 /*************************Py_Code_Generator Version: 0.1-0.14-0.2 @ 2020-10-20*************************/
1287 /********************** (C) COPYRIGHT Fudan Microelectronics **** END OF FILE ***********************/
1288