FSL_FEATURE_MCG_PLL_VDIV_BASE (reference) in projects: bsp

Searched refs:FSL_FEATURE_MCG_PLL_VDIV_BASE (Results 1 – 2 of 2) sorted by relevance

/bsp/frdm-k64f/device/MK64F12/
A D	fsl_clock.c	647 mcgpll0clk = (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); in CLOCK_GetPll0Freq() 781 …if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) \|\| (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE +… in CLOCK_CalcPllDiv() 789 if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE) in CLOCK_CalcPllDiv() 794 vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv() 806 if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) in CLOCK_CalcPllDiv() 823 *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE; in CLOCK_CalcPllDiv()
/bsp/frdm-k64f/device/
A D	MK64F12_features.h	`1449 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) macro`

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