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Searched refs:FSMC_Bank_InitStruct (Results 1 – 2 of 2) sorted by relevance

/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_fsmc.c85 … (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ in FSMC_NORSRAM_Bank_Init()
86 … (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \ in FSMC_NORSRAM_Bank_Init()
87 … (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \ in FSMC_NORSRAM_Bank_Init()
88 … (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; in FSMC_NORSRAM_Bank_Init()
90 … FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos; in FSMC_NORSRAM_Bank_Init()
95 … (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ in FSMC_NORSRAM_Bank_Init()
98 … (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; in FSMC_NORSRAM_Bank_Init()
100 … FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos; in FSMC_NORSRAM_Bank_Init()
105 … (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ in FSMC_NORSRAM_Bank_Init()
108 … (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; in FSMC_NORSRAM_Bank_Init()
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/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Inc/
A Dhal_fsmc.h135 void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_…

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