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Searched refs:GCLK_CTRLA_SWRST_Pos (Results 1 – 10 of 10) sorted by relevance

/bsp/microchip/saml10/bsp/include/component/
A Dgclk.h59 #define GCLK_CTRLA_SWRST_Pos 0 /**< (GC… macro
60 #define GCLK_CTRLA_SWRST_Msk (_U_(0x1) << GCLK_CTRLA_SWRST_Pos) /**< (GC…
/bsp/microchip/samc21/bsp/samc21/include/component/
A Dgclk.h56 #define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */ macro
57 #define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dgclk.h56 #define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */ macro
57 #define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dgclk.h56 #define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */ macro
57 #define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
/bsp/microchip/same54/bsp/include/component/
A Dgclk.h56 #define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */ macro
57 #define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
/bsp/microchip/samc21/bsp/hri/
A Dhri_gclk_c21.h145 tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; in hri_gclk_get_CTRLA_SWRST_bit()
/bsp/microchip/saml10/bsp/hri/
A Dhri_gclk_l10.h125 tmp = (tmp & GCLK_CTRLA_SWRST_Msk) >> GCLK_CTRLA_SWRST_Pos; in hri_gclk_get_CTRLA_SWRST_bit()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_gclk_d51.h160 tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; in hri_gclk_get_CTRLA_SWRST_bit()
/bsp/microchip/same54/bsp/hri/
A Dhri_gclk_e54.h160 tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; in hri_gclk_get_CTRLA_SWRST_bit()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_gclk_d51.h160 tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; in hri_gclk_get_CTRLA_SWRST_bit()

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