Home
last modified time | relevance | path

Searched refs:GCLK_SOURCE_FDPLL (Results 1 – 7 of 7) sorted by relevance

/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/
A Dgclk.h69 #define GCLK_SOURCE_FDPLL 8 // FDPLL output macro
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/
A Dgclk.h72 #define GCLK_SOURCE_FDPLL macro
/bsp/microchip/same54/bsp/include/instance/
A Dgclk.h185 #define GCLK_SOURCE_FDPLL 7 // Alias to GCLK_SOURCE_DPLL0 macro
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/instance/
A Dgclk.h185 #define GCLK_SOURCE_FDPLL 7 // Alias to GCLK_SOURCE_DPLL0 macro
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/instance/
A Dgclk.h185 #define GCLK_SOURCE_FDPLL 7 // Alias to GCLK_SOURCE_DPLL0 macro
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/
A Dclock_feature.h537 SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL,
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/
A Dclock_feature.h539 SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL,

Completed in 18 milliseconds