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Searched refs:GCLK_SYNCBUSY_GENCTRL5_Pos (Results 1 – 8 of 8) sorted by relevance

/bsp/microchip/samc21/bsp/samc21/include/component/
A Dgclk.h101 #define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generato… macro
102 #define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dgclk.h104 #define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generato… macro
105 #define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dgclk.h104 #define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generato… macro
105 #define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
/bsp/microchip/same54/bsp/include/component/
A Dgclk.h104 #define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generato… macro
105 #define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
/bsp/microchip/samc21/bsp/hri/
A Dhri_gclk_c21.h101 return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; in hri_gclk_get_SYNCBUSY_GENCTRL5_bit()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_gclk_d51.h101 return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; in hri_gclk_get_SYNCBUSY_GENCTRL5_bit()
/bsp/microchip/same54/bsp/hri/
A Dhri_gclk_e54.h101 return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; in hri_gclk_get_SYNCBUSY_GENCTRL5_bit()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_gclk_d51.h101 return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; in hri_gclk_get_SYNCBUSY_GENCTRL5_bit()

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