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Searched refs:GENCTRL (Results 1 – 14 of 14) sorted by relevance

/bsp/microchip/samc21/bsp/hri/
A Dhri_gclk_c21.h207 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
216 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
219 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
251 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()
260 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()
263 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()
295 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OOV_bit()
304 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_OOV_bit()
307 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_OOV_bit()
339 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OE_bit()
[all …]
/bsp/microchip/saml10/bsp/hri/
A Dhri_gclk_l10.h187 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
196 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
199 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
231 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()
240 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()
243 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()
275 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OOV_bit()
284 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_OOV_bit()
287 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_OOV_bit()
319 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OE_bit()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_gclk_d51.h222 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
231 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
234 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
266 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()
275 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()
278 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()
310 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OOV_bit()
319 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_OOV_bit()
322 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_OOV_bit()
354 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OE_bit()
[all …]
/bsp/microchip/same54/bsp/hri/
A Dhri_gclk_e54.h222 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
231 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
234 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
266 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()
275 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()
278 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()
310 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OOV_bit()
319 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_OOV_bit()
322 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_OOV_bit()
354 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OE_bit()
[all …]
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_gclk_d51.h222 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_GENEN_bit()
231 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_GENEN_bit()
234 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_GENEN_bit()
266 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_IDC_bit()
275 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_IDC_bit()
278 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_IDC_bit()
310 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OOV_bit()
319 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_write_GENCTRL_OOV_bit()
322 ((Gclk *)hw)->GENCTRL[index].reg = tmp; in hri_gclk_write_GENCTRL_OOV_bit()
354 tmp = ((Gclk *)hw)->GENCTRL[index].reg; in hri_gclk_get_GENCTRL_OE_bit()
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/
A Dgclk.c190 GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); in system_gclk_gen_set_config()
213 *((uint8_t*)&GCLK->GENCTRL.reg) = generator; in system_gclk_gen_enable()
219 GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN; in system_gclk_gen_enable()
242 *((uint8_t*)&GCLK->GENCTRL.reg) = generator; in system_gclk_gen_disable()
248 GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN; in system_gclk_gen_disable()
249 while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) { in system_gclk_gen_disable()
273 *((uint8_t*)&GCLK->GENCTRL.reg) = generator; in system_gclk_gen_is_enabled()
275 enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); in system_gclk_gen_is_enabled()
302 *((uint8_t*)&GCLK->GENCTRL.reg) = generator; in system_gclk_gen_get_hz()
311 *((uint8_t*)&GCLK->GENCTRL.reg) = generator; in system_gclk_gen_get_hz()
[all …]
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/
A Dgclk.c190 GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); in system_gclk_gen_set_config()
213 *((uint8_t*)&GCLK->GENCTRL.reg) = generator; in system_gclk_gen_enable()
219 GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN; in system_gclk_gen_enable()
242 *((uint8_t*)&GCLK->GENCTRL.reg) = generator; in system_gclk_gen_disable()
248 GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN; in system_gclk_gen_disable()
249 while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) { in system_gclk_gen_disable()
273 *((uint8_t*)&GCLK->GENCTRL.reg) = generator; in system_gclk_gen_is_enabled()
275 enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); in system_gclk_gen_is_enabled()
302 *((uint8_t*)&GCLK->GENCTRL.reg) = generator; in system_gclk_gen_get_hz()
311 *((uint8_t*)&GCLK->GENCTRL.reg) = generator; in system_gclk_gen_get_hz()
[all …]
/bsp/microchip/saml10/bsp/include/component/
A Dgclk.h81 …uint32_t GENCTRL:5; /**< bit: 2..6 Generic Clock Generator Control 4 Synchroniz… member
229 …__IO GCLK_GENCTRL_Type GENCTRL[5]; /**< Offset: 0x20 (R/W 32) Generic Clock Gene… member
/bsp/microchip/samc21/bsp/samc21/include/component/
A Dgclk.h79 …uint32_t GENCTRL:9; /*!< bit: 2..10 Generic Clock Generator Control x Synchronization Bus… member
241 …__IO GCLK_GENCTRL_Type GENCTRL[9]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Genera… member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dgclk.h82 …uint32_t GENCTRL:12; /*!< bit: 2..13 Generic Clock Generator Control x Synchronization Bus… member
264 …__IO GCLK_GENCTRL_Type GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Genera… member
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dgclk.h82 …uint32_t GENCTRL:12; /*!< bit: 2..13 Generic Clock Generator Control x Synchronization Bus… member
264 …__IO GCLK_GENCTRL_Type GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Genera… member
/bsp/microchip/same54/bsp/include/component/
A Dgclk.h82 …uint32_t GENCTRL:12; /*!< bit: 2..13 Generic Clock Generator Control x Synchronization Bus… member
264 …__IO GCLK_GENCTRL_Type GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Genera… member
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/
A Dgclk.h303 …__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generat… member
/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/component/
A Dgclk.h318 …__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generat… member

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