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Searched refs:GET_BITS (Results 1 – 17 of 17) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/
A Dclk_factors.c89 if (GET_BITS(factor->lock_bit, 1, reg)) in sunxi_clk_is_lock()
136 if (GET_BITS(config->enshift, 1, reg)) in sunxi_clk_fators_enable()
210 if (!GET_BITS(config->enshift, 1, reg)) in sunxi_clk_fators_disable()
267 val = GET_BITS(config->enshift, 1, reg); in sunxi_clk_fators_is_enabled()
304 factor_val.factorn = GET_BITS(config->nshift, config->nwidth, reg); in sunxi_clk_factors_recalc_rate()
313 factor_val.factork = GET_BITS(config->kshift, config->kwidth, reg); in sunxi_clk_factors_recalc_rate()
322 factor_val.factorm = GET_BITS(config->mshift, config->mwidth, reg); in sunxi_clk_factors_recalc_rate()
331 factor_val.factorp = GET_BITS(config->pshift, config->pwidth, reg); in sunxi_clk_factors_recalc_rate()
358 factor_val.frac_mode = GET_BITS(config->modeshift, 1, reg); in sunxi_clk_factors_recalc_rate()
359 factor_val.frac_freq = GET_BITS(config->outshift, 1, reg); in sunxi_clk_factors_recalc_rate()
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A Dclk_periph.c53 *parent_index = GET_BITS(periph->mux.shift, periph->mux.width, reg); in sunxi_clk_periph_get_parent()
221 state &= GET_BITS(gate->bus_shift, 1, reg); in sunxi_clk_periph_is_enabled()
228 state &= GET_BITS(gate->enb_shift, 1, reg); in sunxi_clk_periph_is_enabled()
235 state &= GET_BITS(gate->rst_shift, 1, reg); in sunxi_clk_periph_is_enabled()
242 state &= GET_BITS(gate->ddr_shift, 1, reg); in sunxi_clk_periph_is_enabled()
391 div_m = GET_BITS(divider->mshift, divider->mwidth, reg); in sunxi_clk_periph_recalc_rate()
395 div_n = GET_BITS(divider->nshift, divider->nwidth, reg); in sunxi_clk_periph_recalc_rate()
A Dclk.h86 #define GET_BITS(shift, width, reg) \ macro
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/
A Dgd32vf103_can.h538 #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U)
541 #define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U)
544 #define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U)
547 #define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
550 #define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
553 #define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
556 #define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
559 #define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
562 #define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
565 #define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
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A Dgd32vf103_bkp.h165 #define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15)
A Dgd32vf103_i2c.h267 #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
/bsp/n32/libraries/n32_drivers/
A Ddrv_hwtimer.c150 #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) macro
175 clkpre = GET_BITS(RCC->CFG, 8, 10); in n32_hwtimer_control()
180 clkpre = GET_BITS(RCC->CFG, 11, 13); in n32_hwtimer_control()
255 clkpre = GET_BITS(RCC->CFG, 8, 10); in n32_hwtimer_init()
260 clkpre = GET_BITS(RCC->CFG, 11, 13); in n32_hwtimer_init()
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/
A Dgd32vf103_rcu.c1017 sws = GET_BITS(RCU_CFG0, 2, 3); in rcu_clock_freq_get()
1054 pllmf = GET_BITS(RCU_CFG0, 18, 21); in rcu_clock_freq_get()
1079 idx = GET_BITS(RCU_CFG0, 4, 7); in rcu_clock_freq_get()
1084 idx = GET_BITS(RCU_CFG0, 8, 10); in rcu_clock_freq_get()
1089 idx = GET_BITS(RCU_CFG0, 11, 13); in rcu_clock_freq_get()
A Dgd32vf103_adc.c425 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); in adc_inserted_channel_config()
469 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); in adc_inserted_channel_offset_config()
A Dgd32vf103_usart.c261 return (uint16_t)(GET_BITS(USART_DATA(usart_periph), 0U, 8U)); in usart_data_receive()
/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/
A Ddrv_hwtimer.c94 clkpre = GET_BITS(RCU_CFG0, 8, 10); in gd32_hwtimer_control()
99 clkpre = GET_BITS(RCU_CFG0, 11, 13); in gd32_hwtimer_control()
A Ddrv_pwm.c95 clkpre = GET_BITS(RCU_CFG0, 8, 10); in gd32_get_pwm_clk()
100 clkpre = GET_BITS(RCU_CFG0, 11, 13); in gd32_get_pwm_clk()
/bsp/allwinner/libraries/sunxi-hal/hal/source/tpadc/
A Dcommon_tpadc.h43 #define GET_BITS(shift, width, reg) \ macro
/bsp/allwinner/libraries/sunxi-hal/include/hal/
A Dsunxi_hal_pwm.h68 #define GET_BITS(shift, width, reg) \ macro
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/
A Dsystem_gd32vf103.c196 scss = GET_BITS(RCU_CFG0, 2, 3); in SystemCoreClockUpdate()
239 pllmf = GET_BITS(RCU_CFG0, 18, 21); in SystemCoreClockUpdate()
266 idx = GET_BITS(RCU_CFG0, 4, 7); in SystemCoreClockUpdate()
A Dgd32vf103.h190 #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) macro
/bsp/allwinner/libraries/sunxi-hal/hal/source/disp2/disp/de/
A Dinclude.h70 #define GET_BITS(shift, width, reg) \ macro

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