1 /** @file reg_dma.h 2 * @brief DMA Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * . 10 * which are relevant for the DMA driver. 11 */ 12 13 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 14 15 #ifndef __REG_DMA_H__ 16 #define __REG_DMA_H__ 17 18 #include "sys_common.h" 19 20 /* USER CODE BEGIN (0) */ 21 /* USER CODE END */ 22 23 /* DMA Register Frame Definition */ 24 /** @struct dmaBase 25 * @brief DMA Register Frame Definition 26 * 27 * This type is used to access the DMA Registers. 28 */ 29 /** @struct dmaBASE_t 30 * @brief DMA Register Definition 31 * 32 * This structure is used to access the DMA module egisters. 33 */ 34 typedef volatile struct dmaBase 35 { 36 37 uint32 GCTRL; /**< 0x0000: Global Control Register */ 38 uint32 PEND; /**< 0x0004: Channel Pending Register */ 39 uint32 FBREG; /**< 0x0008: Fall Back Register */ 40 uint32 DMASTAT; /**< 0x000C: Status Register */ 41 uint32 rsvd1; /**< 0x0010: Reserved */ 42 uint32 HWCHENAS; /**< 0x0014: HW Channel Enable Set */ 43 uint32 rsvd2; /**< 0x0018: Reserved */ 44 uint32 HWCHENAR; /**< 0x001C: HW Channel Enable Reset */ 45 uint32 rsvd3; /**< 0x0020: Reserved */ 46 uint32 SWCHENAS; /**< 0x0024: SW Channel Enable Set */ 47 uint32 rsvd4; /**< 0x0028: Reserved */ 48 uint32 SWCHENAR; /**< 0x002C: SW Channel Enable Reset */ 49 uint32 rsvd5; /**< 0x0030: Reserved */ 50 uint32 CHPRIOS; /**< 0x0034: Channel Priority Set */ 51 uint32 rsvd6; /**< 0x0038: Reserved */ 52 uint32 CHPRIOR; /**< 0x003C: Channel Priority Reset */ 53 uint32 rsvd7; /**< 0x0040: Reserved */ 54 uint32 GCHIENAS; /**< 0x0044: Global Channel Interrupt Enable Set */ 55 uint32 rsvd8; /**< 0x0048: Reserved */ 56 uint32 GCHIENAR; /**< 0x004C: Global Channel Interrupt Enable Set */ 57 uint32 rsvd9; /**< 0x0050: Reserved */ 58 uint32 DREQASI[8U];/**< 0x0054 - 0x70: DMA Request Assignment Register */ 59 uint32 rsvd10[8U];/**< 0x0074 - 0x90: Reserved */ 60 uint32 PAR[4U]; /**< 0x0094 - 0xA0: Port Assignment Register */ 61 uint32 rsvd11[4U];/**< 0x00A4 - 0xB0: Reserved */ 62 uint32 FTCMAP; /**< 0x00B4: FTC Interrupt Mapping Register */ 63 uint32 rsvd12; /**< 0x00B8: Reserved */ 64 uint32 LFSMAP; /**< 0x00BC: LFS Interrupt Mapping Register */ 65 uint32 rsvd13; /**< 0x00C0: Reserved */ 66 uint32 HBCMAP; /**< 0x00C4: HBC Interrupt Mapping Register */ 67 uint32 rsvd14; /**< 0x00C8: Reserved */ 68 uint32 BTCMAP; /**< 0x00CC: BTC Interrupt Mapping Register */ 69 uint32 rsvd15; /**< 0x00D0: Reserved */ 70 uint32 BERMAP; /**< 0x00D4: BER Interrupt Mapping Register */ 71 uint32 rsvd16; /**< 0x00D8: Reserved */ 72 uint32 FTCINTENAS; /**< 0x00DC: FTC Interrupt Enable Set */ 73 uint32 rsvd17; /**< 0x00E0: Reserved */ 74 uint32 FTCINTENAR; /**< 0x00E4: FTC Interrupt Enable Reset */ 75 uint32 rsvd18; /**< 0x00E8: Reserved */ 76 uint32 LFSINTENAS; /**< 0x00EC: LFS Interrupt Enable Set */ 77 uint32 rsvd19; /**< 0x00F0: Reserved */ 78 uint32 LFSINTENAR; /**< 0x00F4: LFS Interrupt Enable Reset */ 79 uint32 rsvd20; /**< 0x00F8: Reserved */ 80 uint32 HBCINTENAS; /**< 0x00FC: HBC Interrupt Enable Set */ 81 uint32 rsvd21; /**< 0x0100: Reserved */ 82 uint32 HBCINTENAR; /**< 0x0104: HBC Interrupt Enable Reset */ 83 uint32 rsvd22; /**< 0x0108: Reserved */ 84 uint32 BTCINTENAS; /**< 0x010C: BTC Interrupt Enable Set */ 85 uint32 rsvd23; /**< 0x0110: Reserved */ 86 uint32 BTCINTENAR; /**< 0x0114: BTC Interrupt Enable Reset */ 87 uint32 rsvd24; /**< 0x0118: Reserved */ 88 uint32 GINTFLAG; /**< 0x011C: Global Interrupt Flag Register */ 89 uint32 rsvd25; /**< 0x0120: Reserved */ 90 uint32 FTCFLAG; /**< 0x0124: FTC Interrupt Flag Register */ 91 uint32 rsvd26; /**< 0x0128: Reserved */ 92 uint32 LFSFLAG; /**< 0x012C: LFS Interrupt Flag Register */ 93 uint32 rsvd27; /**< 0x0130: Reserved */ 94 uint32 HBCFLAG; /**< 0x0134: HBC Interrupt Flag Register */ 95 uint32 rsvd28; /**< 0x0138: Reserved */ 96 uint32 BTCFLAG; /**< 0x013C: BTC Interrupt Flag Register */ 97 uint32 rsvd29; /**< 0x0140: Reserved */ 98 uint32 BERFLAG; /**< 0x0144: BER Interrupt Flag Register */ 99 uint32 rsvd30; /**< 0x0148: Reserved */ 100 uint32 FTCAOFFSET; /**< 0x014C: FTCA Interrupt Channel Offset Register */ 101 uint32 LFSAOFFSET; /**< 0x0150: LFSA Interrupt Channel Offset Register */ 102 uint32 HBCAOFFSET; /**< 0x0154: HBCA Interrupt Channel Offset Register */ 103 uint32 BTCAOFFSET; /**< 0x0158: BTCA Interrupt Channel Offset Register */ 104 uint32 BERAOFFSET; /**< 0x015C: BERA Interrupt Channel Offset Register */ 105 uint32 FTCBOFFSET; /**< 0x0160: FTCB Interrupt Channel Offset Register */ 106 uint32 LFSBOFFSET; /**< 0x0164: LFSB Interrupt Channel Offset Register */ 107 uint32 HBCBOFFSET; /**< 0x0168: HBCB Interrupt Channel Offset Register */ 108 uint32 BTCBOFFSET; /**< 0x016C: BTCB Interrupt Channel Offset Register */ 109 uint32 BERBOFFSET; /**< 0x0170: BERB Interrupt Channel Offset Register */ 110 uint32 rsvd31; /**< 0x0174: Reserved */ 111 uint32 PTCRL; /**< 0x0178: Port Control Register */ 112 uint32 RTCTRL; /**< 0x017C: RAM Test Control Register */ 113 uint32 DCTRL; /**< 0x0180: Debug Control */ 114 uint32 WPR; /**< 0x0184: Watch Point Register */ 115 uint32 WMR; /**< 0x0188: Watch Mask Register */ 116 uint32 PAACSADDR; /**< 0x018C: */ 117 uint32 PAACDADDR; /**< 0x0190: */ 118 uint32 PAACTC; /**< 0x0194: */ 119 uint32 PBACSADDR; /**< 0x0198: Port B Active Channel Source Address Register */ 120 uint32 PBACDADDR; /**< 0x019C: Port B Active Channel Destination Address Register */ 121 uint32 PBACTC; /**< 0x01A0: Port B Active Channel Transfer Count Register */ 122 uint32 rsvd32; /**< 0x01A4: Reserved */ 123 uint32 DMAPCR; /**< 0x01A8: Parity Control Register */ 124 uint32 DMAPAR; /**< 0x01AC: DMA Parity Error Address Register */ 125 uint32 DMAMPCTRL; /**< 0x01B0: DMA Memory Protection Control Register */ 126 uint32 DMAMPST; /**< 0x01B4: DMA Memory Protection Status Register */ 127 struct 128 { 129 uint32 STARTADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region Start Address Register */ 130 uint32 ENDADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region Start Address Register */ 131 }DMAMPR[4U]; 132 } dmaBASE_t; 133 134 135 /** @def dmaREG 136 * @brief DMA1 Register Frame Pointer 137 * 138 * This pointer is used by the DMA driver to access the DMA module registers. 139 */ 140 #define dmaREG ((dmaBASE_t *)0xFFFFF000U) 141 142 /* USER CODE BEGIN (1) */ 143 /* USER CODE END */ 144 145 146 #endif 147