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Searched refs:GLB_BASE (Results 1 – 25 of 35) sorted by relevance

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/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/
A Dbl702_glb.c2068 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); in GLB_SWAP_EMAC_CAM_Pin()
2730 BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); in GLB_Power_Off_DLL()
2766 BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); in GLB_Power_On_DLL()
2771 BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); in GLB_Power_On_DLL()
2776 BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); in GLB_Power_On_DLL()
2783 BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); in GLB_Power_On_DLL()
2790 BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); in GLB_Power_On_DLL()
2820 BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); in GLB_Enable_DLL_All_Clks()
2862 BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); in GLB_Enable_DLL_Clk()
2889 BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal); in GLB_Disable_DLL_All_Clks()
[all …]
A Dbl702_clock.c108 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_XClk_Sel_Val()
118 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_Root_Clk_Sel_Val()
164 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_HClk_Div_Val()
173 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_Peri_BClk_Div_Val()
305 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); in Clock_Get_UART_Div_Val()
320 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); in Clock_Get_SPI_Div_Val()
335 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); in Clock_Get_I2C_Div_Val()
471 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); in Clock_Get_IR_Div_Val()
491 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); in Clock_Get_CAM_Clk_Sel_Val()
500 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1); in Clock_Get_CAM_Div_Val()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/
A Dbl602_glb.c167 BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); in GLB_Set_System_CLK_Div()
176 BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal); in GLB_Set_System_CLK_Div()
1338 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); in GLB_UART_Sig_Swap_Set()
1340 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); in GLB_UART_Sig_Swap_Set()
1361 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); in GLB_JTAG_Sig_Swap_Set()
1380 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); in GLB_Swap_SPI_0_MOSI_With_MISO()
1401 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); in GLB_Set_SPI_0_ACT_MOD_Sel()
1422 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); in GLB_Select_Internal_Flash()
1444 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); in GLB_Select_External_Flash()
1466 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); in GLB_Deswap_Flash_Pin()
[all …]
A Dbl602_clock.c139 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_XClk_Sel_Val()
149 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_Root_Clk_Sel_Val()
195 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_MCU_HClk_Div_Val()
204 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0); in Clock_Get_Peri_BClk_Div_Val()
308 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); in Clock_Get_UART_Div_Val()
323 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); in Clock_Get_SPI_Div_Val()
338 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3); in Clock_Get_I2C_Div_Val()
465 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); in Clock_Get_IR_Div_Val()
474 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); in Clock_Get_SF_Clk_Sel2_Val()
514 tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2); in Clock_Get_SF_Clk_Sel_Val()
[all …]
A Dbl602_aon.c470 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); in AON_LowPower_Enter_PDS0()
473 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal); in AON_LowPower_Enter_PDS0()
516 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); in AON_LowPower_Exit_PDS0()
519 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal); in AON_LowPower_Exit_PDS0()
A Dbl602_pds.c206 tmpVal = BL_RD_REG(GLB_BASE, GLB_MBIST_CTL); in PDS_RAM_Config()
212 BL_WR_REG(GLB_BASE, GLB_MBIST_CTL, tmpVal); in PDS_RAM_Config()
217 tmpVal = BL_RD_REG(GLB_BASE, GLB_MBIST_CTL); in PDS_RAM_Config()
222 BL_WR_REG(GLB_BASE, GLB_MBIST_CTL, tmpVal); in PDS_RAM_Config()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/
A Dbl616_glb.c474 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in GLB_Power_On_XTAL_And_PLL_CLK()
476 BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); in GLB_Power_On_XTAL_And_PLL_CLK()
956 BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); in GLB_Set_MCU_System_CLK_Div()
961 BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); in GLB_Set_MCU_System_CLK_Div()
965 BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal); in GLB_Set_MCU_System_CLK_Div()
1307 BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); in GLB_Set_IR_CLK()
1311 BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); in GLB_Set_IR_CLK()
1319 BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); in GLB_Set_IR_CLK()
1455 BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal); in GLB_Set_SF_CLK()
1490 BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal); in GLB_Set_SF_CLK()
[all …]
A Dbl616_glb_gpio.c560 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143); in GPIO_FIFO_IRQHandler()
694 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143); in GLB_GPIO_Fifo_Init()
701 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal); in GLB_GPIO_Fifo_Init()
703 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142); in GLB_GPIO_Fifo_Init()
710 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal); in GLB_GPIO_Fifo_Init()
770 …BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, BL_SET_REG_BIT(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO… in GLB_GPIO_Fifo_Clear()
792 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143); in GLB_GPIO_Fifo_IntMask()
844 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal); in GLB_GPIO_Fifo_IntMask()
890 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal); in GLB_GPIO_Fifo_IntClear()
943 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal); in GLB_GPIO_Fifo_Enable()
[all …]
A Dbl616_clock.c368 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in Clock_Get_MCU_HClk_Div_Val()
377 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in Clock_Get_Peri_BClk_Div_Val()
563 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in Clock_Get_IR_Div_Val()
572 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Clk_Sel2_Val()
615 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Clk_Sel_Val()
624 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Div_Val()
644 tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); in Clock_Get_SPI_Clk_Sel_Val()
653 tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); in Clock_Get_SPI_Div_Val()
673 tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0); in Clock_Get_DBI_Clk_Sel_Val()
682 tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0); in Clock_Get_DBI_Div_Val()
[all …]
A Dbl616_romapi_patch.c1709 tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV1); in GLB_Get_Flash_Id_Value()
1959 BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal); in GLB_Set_ADC_CLK()
1964 BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal); in GLB_Set_ADC_CLK()
1972 BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal); in GLB_Set_ADC_CLK()
1998 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in GLB_Set_IR_CLK()
2000 BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); in GLB_Set_IR_CLK()
2002 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in GLB_Set_IR_CLK()
2004 BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); in GLB_Set_IR_CLK()
2006 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in GLB_Set_IR_CLK()
2012 BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); in GLB_Set_IR_CLK()
[all …]
A Dbl616_aon.c522 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); in AON_LowPower_Enter_PDS0()
525 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal); in AON_LowPower_Enter_PDS0()
565 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); in AON_LowPower_Exit_PDS0()
568 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal); in AON_LowPower_Exit_PDS0()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/
A Dbl808_glb.c1059 BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); in GLB_Power_On_XTAL_And_PLL_CLK()
1691 BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); in GLB_Set_MCU_System_CLK_Div()
1696 BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); in GLB_Set_MCU_System_CLK_Div()
2955 BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); in GLB_Set_IR_CLK()
2959 BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); in GLB_Set_IR_CLK()
2967 BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); in GLB_Set_IR_CLK()
3016 BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal); in GLB_IR_LED_Driver_Enable()
3036 BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal); in GLB_IR_LED_Driver_Disable()
3163 BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal); in GLB_Set_SF_CLK()
3198 BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal); in GLB_Set_SF_CLK()
[all …]
A Dbl808_glb_gpio.c553 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143); in GPIO_FIFO_IRQHandler()
687 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143); in GLB_GPIO_Fifo_Init()
694 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal); in GLB_GPIO_Fifo_Init()
696 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142); in GLB_GPIO_Fifo_Init()
703 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal); in GLB_GPIO_Fifo_Init()
763 …BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, BL_SET_REG_BIT(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO… in GLB_GPIO_Fifo_Clear()
785 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143); in GLB_GPIO_Fifo_IntMask()
837 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal); in GLB_GPIO_Fifo_IntMask()
883 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal); in GLB_GPIO_Fifo_IntClear()
936 BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal); in GLB_GPIO_Fifo_Enable()
[all …]
A Dbl808_clock.c689 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in Clock_Get_MCU_HClk_Div_Val()
698 tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); in Clock_Get_Peri_BClk_Div_Val()
935 tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0); in Clock_Get_EMI_Clk_Div_Val()
944 tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0); in Clock_Get_EMI_Clk_Sel_Val()
1298 tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); in Clock_Get_IR_Div_Val()
1307 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Clk_Sel2_Val()
1350 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Clk_Sel_Val()
1359 tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); in Clock_Get_SF_Div_Val()
1379 tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); in Clock_Get_SPI_Clk_Sel_Val()
1388 tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); in Clock_Get_SPI_Div_Val()
[all …]
A Dbl808_aon.c462 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); in AON_LowPower_Enter_PDS0()
465 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal); in AON_LowPower_Enter_PDS0()
505 tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); in AON_LowPower_Exit_PDS0()
508 BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal); in AON_LowPower_Exit_PDS0()
A Dbl808_uhs_phy.c328 tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS); in Psram_UHS_Init_Override()
330 BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal); in Psram_UHS_Init_Override()
395 BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); in power_up_uhspll()
419 tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); in power_up_ldo12uhs()
422 BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); in power_up_ldo12uhs()
634 tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); in uhs_phy_pwr_down()
636 BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); in uhs_phy_pwr_down()
638 tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); in uhs_phy_pwr_down()
640 BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); in uhs_phy_pwr_down()
645 tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); in uhs_phy_pwr_down()
[all …]
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/
A Dsystem_bl702.c49 tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); in SystemInit()
51 BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); in SystemInit()
55 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); in SystemInit()
57 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); in SystemInit()
86 tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO); in SystemInit()
92 BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal); in SystemInit()
94 BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, 0xffffffff); in SystemInit()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/
A Dsystem_bl602.c43 tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC); in SystemInit()
45 BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal); in SystemInit()
49 tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); in SystemInit()
51 BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); in SystemInit()
66 BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, 0xffffffff); in SystemInit()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/
A Dsystem_bl808.c107 BL_WR_REG(GLB_BASE, GLB_UART_CFG1, 0xffffffff); in SystemInit()
108 BL_WR_REG(GLB_BASE, GLB_UART_CFG2, 0x0000ffff); in SystemInit()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/
A Dsystem_bl616.c133 BL_WR_REG(GLB_BASE, GLB_UART_CFG1, 0xffffffff); in SystemInit()
134 BL_WR_REG(GLB_BASE, GLB_UART_CFG2, 0x0000ffff); in SystemInit()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/
A Dbl602_memorymap.h40 #define GLB_BASE ((uint32_t)0x40000000) macro
A Ddevice_table.c16 .reg_base = GLB_BASE,
30 .reg_base = GLB_BASE,
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/
A Ddevice_table.c16 .reg_base = GLB_BASE,
30 .reg_base = GLB_BASE,
A Dbl702_memorymap.h49 #define GLB_BASE ((uint32_t)0x40000000) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/
A Ddevice_table.c21 .reg_base = GLB_BASE,
35 .reg_base = GLB_BASE,
481 .reg_base = GLB_BASE,

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