Home
last modified time | relevance | path

Searched refs:GPIO_BASE (Results 1 – 25 of 87) sorted by relevance

1234

/bsp/raspberry-pi/raspi4-32/driver/
A Ddrv_gpio.c30 gpfsel = GPIO_REG_GPFSEL0(GPIO_BASE); in raspi_get_pin_state()
411 GPIO_REG_GPREN0(GPIO_BASE) = 0x0; in rt_hw_gpio_init()
412 GPIO_REG_GPREN1(GPIO_BASE) = 0x0; in rt_hw_gpio_init()
414 GPIO_REG_GPFEN0(GPIO_BASE) = 0x0; in rt_hw_gpio_init()
415 GPIO_REG_GPFEN1(GPIO_BASE) = 0x0; in rt_hw_gpio_init()
417 GPIO_REG_GPHEN0(GPIO_BASE) = 0x0; in rt_hw_gpio_init()
418 GPIO_REG_GPHEN1(GPIO_BASE) = 0x0; in rt_hw_gpio_init()
420 GPIO_REG_GPAREN0(GPIO_BASE) = 0x0; in rt_hw_gpio_init()
421 GPIO_REG_GPAREN1(GPIO_BASE) = 0x0; in rt_hw_gpio_init()
423 GPIO_REG_GPAFEN0(GPIO_BASE) = 0x0; in rt_hw_gpio_init()
[all …]
A Draspi4.h31 #define GPIO_BASE (PER_BASE + GPIO_BASE_OFFSET) macro
/bsp/raspberry-pi/raspi2/driver/
A Dbcm283x.h12 #define GPIO_BASE (PER_BASE + 0x200000) macro
13 #define GPIO_GPFSEL0 HWREG32(GPIO_BASE + 0x00) /* GPIO Function Select 0 32bit R/W */
14 #define GPIO_GPFSEL1 HWREG32(GPIO_BASE + 0x04) /* GPIO Function Select 1 32bit R/W */
15 #define GPIO_GPFSEL2 HWREG32(GPIO_BASE + 0x08) /* GPIO Function Select 2 32bit R/W */
16 #define GPIO_GPFSEL4 HWREG32(GPIO_BASE + 0x10) /* GPIO Function Select 4 32bit R/W */
17 #define GPIO_GPSET0 HWREG32(GPIO_BASE + 0x1C)
18 #define GPIO_GPCLR0 HWREG32(GPIO_BASE + 0x28)
19 #define GPIO_GPPUD HWREG32(GPIO_BASE + 0x94) /* GPIO Pin Pull-up/down Enable */
20 #define GPIO_GPPUDCLK0 HWREG32(GPIO_BASE + 0x98) /* GPIO Pin Pull-up/down Enable Clock 0 */
21 #define GPIO_GPPUDCLK1 HWREG32(GPIO_BASE + 0x9C) /* GPIO Pin Pull-up/down Enable Clock 1 */
/bsp/beaglebone/drivers/
A Dgpio.c53 static const rt_base_t GPIO_BASE[] = variable
85 static struct am33xx_gpio_irq_param GPIO_PARAMx[sizeof(GPIO_BASE) / sizeof(GPIO_BASE[0])];
149 reg(GPIO_BASE[gpiox] + GPIO_OE) &= ~(1 << pinNumber); in am33xx_pin_mode()
153 reg(GPIO_BASE[gpiox] + GPIO_OE) |= (1 << pinNumber); in am33xx_pin_mode()
165 reg(GPIO_BASE[gpiox] + GPIO_SETDATAOUT) = (1 << pinNumber); in am33xx_pin_write()
169 reg(GPIO_BASE[gpiox] + GPIO_CLEARDATAOUT) = (1 << pinNumber); in am33xx_pin_write()
179 return reg(GPIO_BASE[gpiox] + GPIO_DATAIN) & (1 << pinNumber) ? 1 : 0; in am33xx_pin_read()
188 rt_base_t baseAdd = GPIO_BASE[gpiox]; in am33xx_pin_attach_irq()
298 rt_base_t baseAdd = GPIO_BASE[gpiox]; in am33xx_pin_irq_enable()
/bsp/gd32/risc-v/libraries/gd32_drivers/
A Ddrv_gpio.h36 …Tx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) +…
41 #define PIN_GDPORT(pin) (GPIO_BASE + (0x400u * PIN_PORT(pin)))
/bsp/gd32/arm/libraries/gd32_drivers/
A Ddrv_gpio.h57 …Tx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) +…
62 #define PIN_GDPORT(pin) (GPIO_BASE + (0x400u * PIN_PORT(pin)))
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/
A Dgd32vf103_gpio.h42 #define GPIOA (GPIO_BASE + 0x00000000U)
43 #define GPIOB (GPIO_BASE + 0x00000400U)
44 #define GPIOC (GPIO_BASE + 0x00000800U)
45 #define GPIOD (GPIO_BASE + 0x00000C00U)
46 #define GPIOE (GPIO_BASE + 0x00001000U)
/bsp/nuvoton/libraries/ma35/rtt_port/
A Ddrv_sspcc.c34 SSPCC_SetRealm_GPIO(GPIO_BASE + (j * 0x40), i, SSPCC_SSET_TZNS); in nu_sspcc_init()
/bsp/airm2m/air105/libraries/HAL_Driver/Inc/
A Dair105.h1002 #define GPIO_BASE (AIR105_APB0_BASE + 0xD000) macro
1077 #define GPIO ((GPIO_MODULE_TypeDef *)GPIO_BASE)
1078 #define GPIOA ((GPIO_TypeDef *)GPIO_BASE)
1079 #define GPIOB ((GPIO_TypeDef *)(GPIO_BASE + 0x0010))
1080 #define GPIOC ((GPIO_TypeDef *)(GPIO_BASE + 0x0020))
1081 #define GPIOD ((GPIO_TypeDef *)(GPIO_BASE + 0x0030))
1082 #define GPIOE ((GPIO_TypeDef *)(GPIO_BASE + 0x0040))
1083 #define GPIOF ((GPIO_TypeDef *)(GPIO_BASE + 0x0050))
1084 #define GPIO_GROUP ((GPIO_TypeDef *)GPIO_BASE)
1085 #define GPIO_ALT_GROUP ((__IO uint32_t *)(GPIO_BASE + 0x180))
[all …]
/bsp/loongson/ls2kdev/drivers/
A Dls2k1000.h22 #define GPIO_BASE (0xFFFFFFFFBFE10500) macro
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Include/
A Defm32g880f128.h277 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
319 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
A Defm32g880f32.h277 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
319 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
A Defm32g880f64.h277 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
319 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
A Defm32g890f128.h277 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
319 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
A Defm32g890f32.h277 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
319 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
A Defm32g890f64.h277 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
319 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
/bsp/Vango/v85xx/Libraries/CMSIS/Vango/V85xx/Include/
A Dtarget.h533 #define GPIO_BASE (AHBPERIPH_BASE + 0x00000000) macro
4585 #define IOB_OEN (volatile unsigned *)(GPIO_BASE + 0x00000020)
4586 #define IOB_IE (volatile unsigned *)(GPIO_BASE + 0x00000024)
4587 #define IOB_DAT (volatile unsigned *)(GPIO_BASE + 0x00000028)
4588 #define IOB_ATT (volatile unsigned *)(GPIO_BASE + 0x0000002C)
4589 #define IOB_STS (volatile unsigned *)(GPIO_BASE + 0x00000030)
4590 #define IOC_OEN (volatile unsigned *)(GPIO_BASE + 0x00000040)
4591 #define IOC_IE (volatile unsigned *)(GPIO_BASE + 0x00000044)
4592 #define IOC_DAT (volatile unsigned *)(GPIO_BASE + 0x00000048)
4593 #define IOC_ATT (volatile unsigned *)(GPIO_BASE + 0x0000004C)
[all …]
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Include/
A Defm32gg990f512.h322 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
371 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
A Defm32gg995f1024.h322 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
371 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
A Defm32gg995f512.h322 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
371 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
A Defm32gg980f1024.h322 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
371 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
A Defm32gg980f512.h322 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
371 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
A Defm32gg990f1024.h322 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */ macro
371 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
/bsp/raspberry-pi/raspi4-64/drivers/
A Draspi4.h47 #define GPIO_BASE (gpio_base_addr) macro
/bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/
A Dgd32vf103.h221 #define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address … macro

Completed in 1283 milliseconds

1234