Searched refs:GPLL (Results 1 – 2 of 2) sorted by relevance
| /bsp/rockchip/common/rk_hal/lib/hal/src/cru/ |
| A D | hal_cru_rk2108.c | 40 static struct PLL_SETUP GPLL = { variable
534 s_gpllFreq = HAL_CRU_GetPllFreq(&GPLL); in HAL_CRU_ClkGetFreq()
542 freq = HAL_CRU_GetPllFreq(&GPLL); in HAL_CRU_ClkGetFreq()
633 s_gpllFreq = HAL_CRU_GetPllFreq(&GPLL); in HAL_CRU_ClkSetFreq()
641 error = HAL_CRU_SetPllFreq(&GPLL, rate); in HAL_CRU_ClkSetFreq()
642 s_gpllFreq = HAL_CRU_GetPllFreq(&GPLL); in HAL_CRU_ClkSetFreq()
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| /bsp/rockchip/rk3500/driver/clk/ |
| A D | clk-rk3588.c | 24 GPLL, enumerator
502 [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3588_PLL_CON(112),
2487 rate = rk_pll_get_rate(&rk3588_pll_clks[GPLL], &priv->cru, GPLL); in rk_clk_get_rate()
2691 reg_base += rk3588_pll_clks[GPLL].con_offset; in rk3588_clk_init()
2831 res_rate = rk_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_clk_set_rate()
2832 GPLL, rate); in rk3588_clk_set_rate()
2833 priv->gpll_hz = rk_pll_get_rate(&rk3588_pll_clks[GPLL], in rk3588_clk_set_rate()
2834 priv->cru, GPLL); in rk3588_clk_set_rate()
3193 ret = rk_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru, in rk3588_cru_init()
3194 GPLL, GPLL_HZ); in rk3588_cru_init()
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