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Searched refs:GpioCtrlRegs (Results 1 – 15 of 15) sorted by relevance

/bsp/ti/c28x/libraries/tms320f28379d/common/source/
A DF2837xD_Upp.c100 GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 in InitUpp1Gpio()
101 GpioCtrlRegs.GPAGMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 in InitUpp1Gpio()
102 GpioCtrlRegs.GPAGMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 in InitUpp1Gpio()
113 GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 in InitUpp1Gpio()
114 GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 in InitUpp1Gpio()
115 GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 in InitUpp1Gpio()
116 GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4 in InitUpp1Gpio()
117 GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3 in InitUpp1Gpio()
118 GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2 in InitUpp1Gpio()
119 GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1 in InitUpp1Gpio()
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A DF2837xD_EPwm.c92 GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A in InitEPwm1Gpio()
93 GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B in InitEPwm1Gpio()
124 GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A in InitEPwm2Gpio()
125 GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B in InitEPwm2Gpio()
156 GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A in InitEPwm3Gpio()
157 GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B in InitEPwm3Gpio()
189 GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A in InitEPwm4Gpio()
190 GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B in InitEPwm4Gpio()
221 GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A in InitEPwm5Gpio()
222 GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B in InitEPwm5Gpio()
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A DF2837xD_EQep.c162 GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A in InitEQep1Gpio()
163 GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B in InitEQep1Gpio()
164 GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S in InitEQep1Gpio()
165 GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I in InitEQep1Gpio()
247 GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A in InitEQep2Gpio()
248 GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B in InitEQep2Gpio()
249 GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2S in InitEQep2Gpio()
250 GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2I in InitEQep2Gpio()
357 GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 1; // Configure GPIO28 as EQEP3A in InitEQep3Gpio()
358 GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 2; // Configure GPIO28 as EQEP3A in InitEQep3Gpio()
[all …]
A DF2837xD_I2C.c80 GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; in I2cAGpioConfig()
81 GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; in I2cAGpioConfig()
87 GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 3; in I2cAGpioConfig()
88 GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; in I2cAGpioConfig()
96 GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 1; in I2cAGpioConfig()
112 GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; in I2cAGpioConfig()
113 GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; in I2cAGpioConfig()
149 GpioCtrlRegs.GPCPUD.bit.GPIO91 = 0; in I2cAGpioConfig()
150 GpioCtrlRegs.GPCPUD.bit.GPIO92 = 0; in I2cAGpioConfig()
209 GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; in I2cBGpioConfig()
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A Dusb_hal.c72 GpioCtrlRegs.GPBLOCK.all = 0x00000000; in USBGPIOEnable()
73 GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 1; in USBGPIOEnable()
74 GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 1; in USBGPIOEnable()
77 GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0; in USBGPIOEnable()
79 GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0; in USBGPIOEnable()
82 GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 3; in USBGPIOEnable()
84 GpioCtrlRegs.GPDMUX2.bit.GPIO121 = 3; in USBGPIOEnable()
97 GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 0; in USBGPIODisable()
98 GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 0; in USBGPIODisable()
101 GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 0; in USBGPIODisable()
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A DF2837xD_Spi.c136 GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) in InitSpiaGpio()
140 GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) in InitSpiaGpio()
141 GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) in InitSpiaGpio()
149 GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) in InitSpiaGpio()
151 GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) in InitSpiaGpio()
153 GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) in InitSpiaGpio()
154 GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) in InitSpiaGpio()
163 GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA in InitSpiaGpio()
165 GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA in InitSpiaGpio()
167 GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA in InitSpiaGpio()
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A DF2837xD_Gpio.c70 GpioCtrlRegs.GPALOCK.all = 0x00000000; in InitGpio()
71 GpioCtrlRegs.GPBLOCK.all = 0x00000000; in InitGpio()
72 GpioCtrlRegs.GPCLOCK.all = 0x00000000; in InitGpio()
73 GpioCtrlRegs.GPDLOCK.all = 0x00000000; in InitGpio()
74 GpioCtrlRegs.GPELOCK.all = 0x00000000; in InitGpio()
75 GpioCtrlRegs.GPFLOCK.all = 0x00000000; in InitGpio()
83 gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; in InitGpio()
399 GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95 in GPIO_EnableUnbondedIOPullupsFor176Pin()
400 GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 in GPIO_EnableUnbondedIOPullupsFor176Pin()
402 GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 in GPIO_EnableUnbondedIOPullupsFor176Pin()
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A DF2837xD_Mcbsp.c250 GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; in InitMcbspaGpio()
259 GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; in InitMcbspaGpio()
260 GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; in InitMcbspaGpio()
270 GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; in InitMcbspaGpio()
282 GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; in InitMcbspaGpio()
283 GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; in InitMcbspaGpio()
292 GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; in InitMcbspaGpio()
304 GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; in InitMcbspaGpio()
305 GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; in InitMcbspaGpio()
491 GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2; in InitMcbspbGpio()
[all …]
A DF2837xD_Ipc_Driver_Util.c396 GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95 in IPCBootCPU2()
401 GpioCtrlRegs.GPCCSEL1.bit.GPIO71 = GPIO_MUX_CPU2; in IPCBootCPU2()
406 GpioCtrlRegs.GPCGMUX1.bit.GPIO71 = 0x1; in IPCBootCPU2()
407 GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 0x1; in IPCBootCPU2()
412 GpioCtrlRegs.GPCQSEL1.bit.GPIO71 = 0x3; in IPCBootCPU2()
414 GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95 in IPCBootCPU2()
419 GpioCtrlRegs.GPCCSEL1.bit.GPIO70 = GPIO_MUX_CPU2; in IPCBootCPU2()
424 GpioCtrlRegs.GPCGMUX1.bit.GPIO70 = 0x1; in IPCBootCPU2()
425 GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 0x1; in IPCBootCPU2()
430 GpioCtrlRegs.GPCQSEL1.bit.GPIO70 = 0x3; in IPCBootCPU2()
[all …]
A DF2837xD_ECap.c141 GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Select OUTPUTXBAR3 on GPIO5 in InitAPwm1Gpio()
/bsp/ti/c28x/libraries/HAL_Drivers/
A Ddrv_sci.c199 GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; in rt_hw_sci_init()
200 GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; in rt_hw_sci_init()
201 GpioCtrlRegs.GPBGMUX1.bit.GPIO42 = 3; in rt_hw_sci_init()
202 GpioCtrlRegs.GPBGMUX1.bit.GPIO43 = 3; in rt_hw_sci_init()
204 GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; in rt_hw_sci_init()
205 GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; in rt_hw_sci_init()
206 GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0; in rt_hw_sci_init()
207 GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 0; in rt_hw_sci_init()
209 GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 2; in rt_hw_sci_init()
210 GpioCtrlRegs.GPEMUX1.bit.GPIO139 = 2; in rt_hw_sci_init()
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A Ddrv_pwm.c393 GpioCtrlRegs.GPAPUD.all |= 5<<(1-1)*4; /* Disable pull-up(EPWM1A) */ in c28x_hw_pwm_init()
394 GpioCtrlRegs.GPAMUX1.all|= 5<<(1-1)*4; /* Configure as EPWM1A */ in c28x_hw_pwm_init()
428 GpioCtrlRegs.GPAPUD.all |= 5<<(2-1)*4; /* Disable pull-up on (EPWM2A) */ in c28x_hw_pwm_init()
429 GpioCtrlRegs.GPAMUX1.all|= 5<<(2-1)*4; /* Configure as EPWM2A */ in c28x_hw_pwm_init()
463 GpioCtrlRegs.GPAPUD.all |= 5<<(3-1)*4; /* Disable pull-up on (EPWM3A) */ in c28x_hw_pwm_init()
464 GpioCtrlRegs.GPAMUX1.all|= 5<<(3-1)*4; /* Configure as EPWM3A */ in c28x_hw_pwm_init()
498 GpioCtrlRegs.GPAPUD.all |= 5<<(4-1)*4; /* Disable pull-up on (EPWM4A) */ in c28x_hw_pwm_init()
499 GpioCtrlRegs.GPAMUX1.all|= 5<<(4-1)*4; /* Configure as EPWM4A */ in c28x_hw_pwm_init()
A Ddrv_gpio.c103 gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (PIN_PORT(pin))*GPY_CTRL_OFFSET; in c28x_pin_mode()
/bsp/ti/c28x/libraries/tms320f28379d/headers/source/
A DF2837xD_GlobalVariableDefs.c528 #pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile");
530 volatile struct GPIO_CTRL_REGS GpioCtrlRegs; variable
/bsp/ti/c28x/libraries/tms320f28379d/headers/include/
A DF2837xD_gpio.h3868 extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;

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