| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/Device/Holtek/HT32F5xxxx/Source/ |
| A D | system_ht32f5xxxx_04.c | 109 #define HCLK_SRC (2) /*!< 0: N/A 1: N/A 2: HSE, 3: HSI 6: LSE, 7: … macro
170 #if (HCLK_SRC == 2)
176 #elif (HCLK_SRC == 3)
182 #elif (HCLK_SRC == 6)
188 #elif (HCLK_SRC == 7)
275 #if (HCLK_SRC == 7) in SystemInit()
280 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
281 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
284 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2)) in SystemInit()
289 #if ((HSI_ENABLE == 0) && (HCLK_SRC != 3)) in SystemInit()
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| A D | system_ht32f5xxxx_13.c | 101 #define HCLK_SRC (2) /*!< 0: N/A 1: N/A 2: HSE, 3: HSI 6: LSE, 7: … macro
162 #if (HCLK_SRC == 2)
168 #elif (HCLK_SRC == 3)
174 #elif (HCLK_SRC == 6)
180 #elif (HCLK_SRC == 7)
267 #if (HCLK_SRC == 7) in SystemInit()
272 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
273 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
276 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2)) in SystemInit()
281 #if ((HSI_ENABLE == 0) && (HCLK_SRC != 3)) in SystemInit()
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| A D | system_ht32f0006.c | 135 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
241 #if (HCLK_SRC == 1)
247 #elif (HCLK_SRC == 2)
253 #elif (HCLK_SRC == 3)
259 #elif (HCLK_SRC == 6)
265 #elif (HCLK_SRC == 7)
364 #if (HCLK_SRC == 7) in SystemInit()
390 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
391 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
408 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_07.c | 139 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
245 #if (HCLK_SRC == 1)
251 #elif (HCLK_SRC == 2)
257 #elif (HCLK_SRC == 3)
263 #elif (HCLK_SRC == 6)
269 #elif (HCLK_SRC == 7)
368 #if (HCLK_SRC == 7) in SystemInit()
394 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
395 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
412 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5826.c | 139 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
247 #if (HCLK_SRC == 1)
253 #elif (HCLK_SRC == 2)
259 #elif (HCLK_SRC == 3)
265 #elif (HCLK_SRC == 6)
275 #elif (HCLK_SRC == 7)
390 #if (HCLK_SRC == 7) in SystemInit()
416 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
417 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
436 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_01.c | 151 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
259 #if (HCLK_SRC == 1)
265 #elif (HCLK_SRC == 2)
271 #elif (HCLK_SRC == 3)
277 #elif (HCLK_SRC == 6)
287 #elif (HCLK_SRC == 7)
402 #if (HCLK_SRC == 7) in SystemInit()
428 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
429 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
448 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_02.c | 164 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
272 #if (HCLK_SRC == 1)
278 #elif (HCLK_SRC == 2)
284 #elif (HCLK_SRC == 3)
290 #elif (HCLK_SRC == 6)
300 #elif (HCLK_SRC == 7)
415 #if (HCLK_SRC == 7) in SystemInit()
441 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
442 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
461 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_03.c | 155 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
261 #if (HCLK_SRC == 1)
267 #elif (HCLK_SRC == 2)
273 #elif (HCLK_SRC == 3)
279 #elif (HCLK_SRC == 6)
285 #elif (HCLK_SRC == 7)
391 #if (HCLK_SRC == 7) in SystemInit()
427 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
428 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
447 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_05.c | 153 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
258 #if (HCLK_SRC == 1)
264 #elif (HCLK_SRC == 2)
270 #elif (HCLK_SRC == 3)
276 #elif (HCLK_SRC == 6)
282 #elif (HCLK_SRC == 7)
383 #if (HCLK_SRC == 7) in SystemInit()
419 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
420 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
430 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_06.c | 140 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
245 #if (HCLK_SRC == 1)
251 #elif (HCLK_SRC == 2)
257 #elif (HCLK_SRC == 3)
263 #elif (HCLK_SRC == 6)
269 #elif (HCLK_SRC == 7)
370 #if (HCLK_SRC == 7) in SystemInit()
406 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
407 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
417 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_08.c | 148 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
261 #if (HCLK_SRC == 1)
267 #elif (HCLK_SRC == 2)
273 #elif (HCLK_SRC == 3)
279 #elif (HCLK_SRC == 6)
290 #elif (HCLK_SRC == 7)
391 #if (HCLK_SRC == 7) in SystemInit()
427 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
428 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
445 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_09.c | 141 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
246 #if (HCLK_SRC == 1)
252 #elif (HCLK_SRC == 2)
258 #elif (HCLK_SRC == 3)
264 #elif (HCLK_SRC == 6)
270 #elif (HCLK_SRC == 7)
371 #if (HCLK_SRC == 7) in SystemInit()
407 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
408 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
418 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_11.c | 147 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
267 #if (HCLK_SRC == 1)
273 #elif (HCLK_SRC == 2)
279 #elif (HCLK_SRC == 3)
285 #elif (HCLK_SRC == 6)
291 #elif (HCLK_SRC == 7)
392 #if (HCLK_SRC == 7) in SystemInit()
428 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
429 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
439 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_12.c | 139 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
244 #if (HCLK_SRC == 1)
250 #elif (HCLK_SRC == 2)
256 #elif (HCLK_SRC == 3)
262 #elif (HCLK_SRC == 6)
268 #elif (HCLK_SRC == 7)
367 #if (HCLK_SRC == 7) in SystemInit()
403 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
404 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
414 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_14.c | 143 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
248 #if (HCLK_SRC == 1)
254 #elif (HCLK_SRC == 2)
260 #elif (HCLK_SRC == 3)
266 #elif (HCLK_SRC == 6)
272 #elif (HCLK_SRC == 7)
371 #if (HCLK_SRC == 7) in SystemInit()
407 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
408 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
418 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_15.c | 141 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
246 #if (HCLK_SRC == 1)
252 #elif (HCLK_SRC == 2)
258 #elif (HCLK_SRC == 3)
264 #elif (HCLK_SRC == 6)
270 #elif (HCLK_SRC == 7)
369 #if (HCLK_SRC == 7) in SystemInit()
405 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
406 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
416 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_17.c | 142 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
247 #if (HCLK_SRC == 1)
253 #elif (HCLK_SRC == 2)
259 #elif (HCLK_SRC == 3)
265 #elif (HCLK_SRC == 6)
271 #elif (HCLK_SRC == 7)
370 #if (HCLK_SRC == 7) in SystemInit()
406 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
407 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
417 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_18.c | 146 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
252 #if (HCLK_SRC == 1)
258 #elif (HCLK_SRC == 2)
264 #elif (HCLK_SRC == 3)
270 #elif (HCLK_SRC == 6)
276 #elif (HCLK_SRC == 7)
382 #if (HCLK_SRC == 7) in SystemInit()
418 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
419 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
438 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f5xxxx_10.c | 136 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 7: … macro
234 #if (HCLK_SRC == 1)
240 #elif (HCLK_SRC == 2)
246 #elif (HCLK_SRC == 3)
252 #elif (HCLK_SRC == 7)
343 #if (HCLK_SRC == 7) in SystemInit()
379 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
380 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
390 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
395 #if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) in SystemInit()
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| A D | system_ht32f5xxxx_16.c | 139 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 7: … macro
238 #if (HCLK_SRC == 1)
244 #elif (HCLK_SRC == 2)
250 #elif (HCLK_SRC == 3)
256 #elif (HCLK_SRC == 7)
347 #if (HCLK_SRC == 7) in SystemInit()
385 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
386 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
405 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
410 #if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) in SystemInit()
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/Device/Holtek/HT32F1xxxx/Source/ |
| A D | system_ht32f1xxxx_02.c | 143 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
250 #if (HCLK_SRC == 1)
256 #elif (HCLK_SRC == 2)
262 #elif (HCLK_SRC == 3)
268 #elif (HCLK_SRC == 6)
274 #elif (HCLK_SRC == 7)
392 #if (HCLK_SRC == 7) in SystemInit()
422 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
423 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
455 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f1xxxx_03.c | 146 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI 6: LSE, 7: … macro
253 #if (HCLK_SRC == 1)
259 #elif (HCLK_SRC == 2)
265 #elif (HCLK_SRC == 3)
271 #elif (HCLK_SRC == 6)
277 #elif (HCLK_SRC == 7)
385 #if (HCLK_SRC == 7) in SystemInit()
422 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~7UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
423 …while ((HT_CKCU->CKST & 7UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
455 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
[all …]
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| A D | system_ht32f1xxxx_01.c | 136 #define HCLK_SRC (1) /*!< 0: PLL, 1: PLL, 2: HSE, 3: HSI … macro
243 #if (HCLK_SRC == 1)
249 #elif (HCLK_SRC == 2)
255 #elif (HCLK_SRC == 3)
377 …HT_CKCU->GCCR = ((HT_CKCU->GCCR & ~3UL) | HCLK_SRC); /* select CK_SYS source … in SystemInit()
378 …while (((HT_CKCU->CKST >> 30) & 3UL) != HCLK_SRC); /* wait for clock switch complete … in SystemInit()
400 #if ((HSE_ENABLE == 0) && (HCLK_SRC != 2) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 1))) in SystemInit()
405 #if ((HSI_ENABLE == 0) && (HCLK_SRC != 3) && ((PLL_ENABLE == 0) || (PLL_CLK_SRC == 0))) in SystemInit()
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