1 /* 2 * Copyright 2020 GreenWaves Technologies 3 * Copyright 2020 ETH Zurich 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 */ 19 20 21 /*! 22 * @file periph.h 23 * @version 1.0 24 * @date 2017-07-19 25 * @brief CMSIS Peripheral Access Layer for PULP 26 * 27 * CMSIS Peripheral Access Layer for PULP 28 */ 29 30 #ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PERIPH_H_ 31 #define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PERIPH_H_ /**< Symbol preventing repeated inclusion */ 32 33 #include "pmsis_gcc.h" 34 /* ---------------------------------------------------------------------------- 35 -- Interrupt vector numbers 36 ---------------------------------------------------------------------------- */ 37 38 /*! 39 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 40 * @{ 41 */ 42 /** Interrupt Number Definitions */ 43 #define NUMBER_OF_INT_VECTORS 32 /**< Number of interrupts in the Vector table */ 44 45 typedef enum IRQn { 46 FC_NOTIFY_CLUSTER_EVENT = 0, /**< Software event interrupt */ 47 CLUSTER_NOTIFY_FC_EVENT = 1, /**< Software event interrupt */ 48 FC_SW_NOTIFY_BRIDGE_EVENT = 2, /**< Software event interrupt */ 49 FC_SW_NOTIFY_EVENT = 3, /**< Software event interrupt */ 50 CLUSTER_NOTIFY_FC_IRQN = 4, /**< Software event interrupt */ 51 DMA_SW_IRQN = 6, 52 PENDSV_IRQN = 7, /**< Software event U -> M PendSV interrupt */ 53 54 /* Device specific interrupts */ 55 DMA_EVT_IRQN = 8, /**< DMA event interrupt */ 56 DMA_IRQN = 9, /**< DMA interrupt */ 57 FC_TIMER0_IRQN = 10, /**< FC timer0 event interrupt */ 58 SYSTICK_IRQN = 10, /**< PULP U -> M System Tick Interrupt */ 59 FC_TIMER1_IRQN = 11, /**< FC timer1 interrupt */ 60 61 /* misc */ 62 FC_CLK_REF_EVENT = 14, /**< Reference clock edge event */ 63 FC_GPIO_EVENT = 15, /**< GPIO event */ 64 65 /* advanced timer events */ 66 FC_ADV_TIMER0_EVENT = 17, /**< Advanced Timer 0 event */ 67 FC_ADV_TIMER1_EVENT = 18, /**< Advanced Timer 1 event */ 68 FC_ADV_TIMER2_EVENT = 19, /**< Advanced Timer 2 event */ 69 FC_ADV_TIMER3_EVENT = 20, /**< Advanced Timer 3 event */ 70 71 /* CLUSTER_NOT_BUSY_EVENT = 21, */ 72 /* CLUSTER_POK_EVENT = 22, */ 73 /* CLUSTER_CG_OK_EVENT = 23, */ 74 75 /* PICL_OK_EVENT = 24, */ 76 /* SCU_OK_EVENT = 25, */ 77 78 FC_SOC_EVENT = 26, /**< Event unit new event */ 79 80 FC_QUEUE_ERROR_EVENT = 29, /**< Event unit queue overflow event */ 81 82 FC_HP_EVENT1 = 30, 83 FC_HP_EVENT0 = 31 84 } IRQn_Type; 85 86 /*! 87 * @} 88 */ /* end of group Interrupt_vector_numbers */ 89 90 91 /* ---------------------------------------------------------------------------- 92 -- PULP Core Configuration 93 ---------------------------------------------------------------------------- */ 94 95 /*! 96 * @addtogroup PULP_Core_Configuration PULP Core Configuration 97 * @{ 98 */ 99 100 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 101 #define __NVIC_PRIO_BITS 0 /**< Number of priority bits implemented in the NVIC */ 102 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 103 #define __FPU_PRESENT 0 /**< Defines if an FPU is present or not */ 104 105 #include "core_pulp.h" /* Core Peripheral Access Layer */ 106 107 #ifdef FEATURE_CLUSTER 108 #include "core_pulp_cluster.h" /* Cluster Access Layer */ 109 #endif 110 111 /*! 112 * @} 113 */ /* end of group PULP_Core_Configuration */ 114 115 116 /* ---------------------------------------------------------------------------- 117 -- Mapping Information 118 ---------------------------------------------------------------------------- */ 119 120 /*! 121 * @addtogroup Mapping_Information Mapping Information 122 * @{ 123 */ 124 125 /** Mapping Information */ 126 /*! 127 * @addtogroup udma_request 128 * @{ 129 */ 130 131 /******************************************************************************* 132 * Definitions 133 ******************************************************************************/ 134 135 136 /*! 137 * @} 138 */ /* end of group udma_request */ 139 140 141 142 /*! 143 * @} 144 */ /* end of group Mapping_Information */ 145 146 147 /* ---------------------------------------------------------------------------- 148 -- Device Peripheral Access Layer 149 ---------------------------------------------------------------------------- */ 150 /*! 151 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 152 * @{ 153 */ 154 155 /* ---------------------------------------------------------------------------- 156 -- FLL_CTRL Peripheral Access Layer 157 ---------------------------------------------------------------------------- */ 158 159 /*! 160 * @addtogroup FLL_CTRL_Peripheral_Access_Layer FLL_CTRL Peripheral Access Layer 161 * @{ 162 */ 163 164 /** FLL_CTRL - Registers Layout Typedef */ 165 /* TODO: looks like pulp has 3 fll */ 166 typedef struct { 167 __IO uint32_t FLL_STATUS; /**< FLL_CTRL Status register, offset: 0x00 */ 168 __IO uint32_t FLL_CONF1; /**< FLL_CTRL Configuration1 register, offset: 0x04 */ 169 __IO uint32_t FLL_CONF2; /**< FLL_CTRL Configuration2 register, offset: 0x08 */ 170 __IO uint32_t FLL_INTEGRATOR; /**< FLL_CTRL INTEGRATOR register, offset: 0x0C */ 171 } FLL_CTRL_Type; 172 173 /* TODO: removed this register, see if it still exists */ 174 /* __IO uint32_t FLL_CONVERGE;*/ /**< FLL_CTRL Fll Converge register, offset: 0x20 */ 175 176 /* ---------------------------------------------------------------------------- 177 -- FLL_CTRL Register Masks 178 ---------------------------------------------------------------------------- */ 179 180 /*! 181 * @addtogroup FLL_CTRL_Register_Masks FLL_CTRL Register Masks 182 * @{ 183 */ 184 /*! @name FLL_STATUS - FLL_CTRL status register */ 185 #define FLL_CTRL_STATUS_MULTI_FACTOR_MASK (0xFFFFU) 186 #define FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT (0U) 187 #define FLL_CTRL_STATUS_MULTI_FACTOR(x) (((uint32_t)(((uint32_t)(x)) /* << FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT */)) & FLL_CTRL_STATUS_MULTI_FACTOR_MASK) 188 #define READ_FLL_CTRL_STATUS_MULTI_FACTOR(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_STATUS_MULTI_FACTOR_MASK)) /*>> FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT*/) 189 190 /*! @name SOC_CONF1 - FLL_CTRL configuration 1 register */ 191 #define FLL_CTRL_CONF1_MULTI_FACTOR_MASK (0xFFFFU) 192 #define FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT (0U) 193 #define FLL_CTRL_CONF1_MULTI_FACTOR(x) (((uint32_t)(((uint32_t)(x)) /* << FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT */)) & FLL_CTRL_CONF1_MULTI_FACTOR_MASK) 194 #define READ_FLL_CTRL_CONF1_MULTI_FACTOR(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF1_MULTI_FACTOR_MASK)) /*>> FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT*/) 195 196 #define FLL_CTRL_CONF1_DCO_INPUT_MASK (0x3FF0000U) 197 #define FLL_CTRL_CONF1_DCO_INPUT_SHIFT (16U) 198 #define FLL_CTRL_CONF1_DCO_INPUT(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF1_DCO_INPUT_SHIFT)) & FLL_CTRL_CONF1_DCO_INPUT_MASK) 199 #define READ_FLL_CTRL_CONF1_DCO_INPUT(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF1_DCO_INPUT_MASK)) >> FLL_CTRL_CONF1_DCO_INPUT_SHIFT) 200 201 #define FLL_CTRL_CONF1_CLK_OUT_DIV_MASK (0x3C000000U) 202 #define FLL_CTRL_CONF1_CLK_OUT_DIV_SHIFT (26U) 203 #define FLL_CTRL_CONF1_CLK_OUT_DIV(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF1_CLK_OUT_DIV_SHIFT)) & FLL_CTRL_CONF1_CLK_OUT_DIV_MASK) 204 #define READ_FLL_CTRL_CONF1_CLK_OUT_DIV(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF1_CLK_OUT_DIV_MASK)) >> FLL_CTRL_CONF1_CLK_OUT_DIV_SHIFT) 205 206 #define FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK (0x40000000U) 207 #define FLL_CTRL_CONF1_OUTPUT_LOCK_EN_SHIFT (30U) 208 #define FLL_CTRL_CONF1_OUTPUT_LOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF1_OUTPUT_LOCK_EN_SHIFT)) & FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK) 209 #define READ_FLL_CTRL_CONF1_OUTPUT_LOCK_EN(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK)) >> FLL_CTRL_CONF1_OUTPUT_LOCK_EN_SHIFT) 210 211 #define FLL_CTRL_CONF1_MODE_MASK (0x80000000U) 212 #define FLL_CTRL_CONF1_MODE_SHIFT (31U) 213 #define FLL_CTRL_CONF1_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF1_MODE_SHIFT)) & FLL_CTRL_CONF1_MODE_MASK) 214 #define READ_FLL_CTRL_CONF1_MODE(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF1_MODE_MASK)) >> FLL_CTRL_CONF1_MODE_SHIFT) 215 216 /*! @name SOC_CONF2 - FLL_CTRL configuration 2 register */ 217 #define FLL_CTRL_CONF2_LOOPGAIN_MASK (0xFU) 218 #define FLL_CTRL_CONF2_LOOPGAIN_SHIF T (0U) 219 #define FLL_CTRL_CONF2_LOOPGAIN(x) (((uint32_t)(((uint32_t)(x)) /* << FLL_CTRL_CONF2_LOOPGAIN_SHIFT */)) & FLL_CTRL_CONF2_LOOPGAIN_MASK) 220 #define READ_FLL_CTRL_CONF2_LOOPGAIN(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_LOOPGAIN_MASK))/* >> FLL_CTRL_CONF2_LOOPGAIN_SHIFT*/) 221 222 #define FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK (0x3F0U) 223 #define FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT (4U) 224 #define FLL_CTRL_CONF2_DEASSERT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT)) & FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK) 225 #define READ_FLL_CTRL_CONF2_DEASSERT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK)) >> FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT) 226 227 #define FLL_CTRL_CONF2_ASSERT_CYCLES_MASK (0xFC00U) 228 #define FLL_CTRL_CONF2_ASSERT_CYCLES_SHIFT (10U) 229 #define FLL_CTRL_CONF2_ASSERT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_ASSERT_CYCLES_SHIFT)) & FLL_CTRL_CONF2_ASSERT_CYCLES_MASK) 230 #define READ_FLL_CTRL_CONF2_ASSERT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_ASSERT_CYCLES_MASK)) >> FLL_CTRL_CONF2_ASSERT_CYCLES_SHIFT) 231 232 #define FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK (0xFFF0000U) 233 #define FLL_CTRL_CONF2_LOCK_TOLERANCE_SHIFT (16U) 234 #define FLL_CTRL_CONF2_LOCK_TOLERANCE(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_LOCK_TOLERANCE_SHIFT)) & FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK) 235 #define READ_FLL_CTRL_CONF2_LOCK_TOLERANCE(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK)) >> FLL_CTRL_CONF2_LOCK_TOLERANCE_SHIFT) 236 237 #define FLL_CTRL_CONF2_CONF_CLK_SEL_MASK (0x20000000U) 238 #define FLL_CTRL_CONF2_CONF_CLK_SEL_SHIFT (29U) 239 #define FLL_CTRL_CONF2_CONF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_CONF_CLK_SEL_SHIFT)) & FLL_CTRL_CONF2_CONF_CLK_SEL_MASK) 240 #define READ_FLL_CTRL_CONF2_CONF_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_CONF_CLK_SEL_MASK)) >> FLL_CTRL_CONF2_CONF_CLK_SEL_SHIFT) 241 242 #define FLL_CTRL_CONF2_OPEN_LOOP_MASK (0x40000000U) 243 #define FLL_CTRL_CONF2_OPEN_LOOP_SHIFT (30U) 244 #define FLL_CTRL_CONF2_OPEN_LOOP(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_OPEN_LOOP_SHIFT)) & FLL_CTRL_CONF2_OPEN_LOOP_MASK) 245 #define READ_FLL_CTRL_CONF2_OPEN_LOOP(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_OPEN_LOOP_MASK)) >> FLL_CTRL_CONF2_OPEN_LOOP_SHIFT) 246 247 #define FLL_CTRL_CONF2_DITHERING_MASK (0x80000000U) 248 #define FLL_CTRL_CONF2_DITHERING_SHIFT (31U) 249 #define FLL_CTRL_CONF2_DITHERING(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_DITHERING_SHIFT)) & FLL_CTRL_CONF2_DITHERING_MASK) 250 #define READ_FLL_CTRL_CONF2_DITHERING(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_DITHERING_MASK)) >> FLL_CTRL_CONF2_DITHERING_SHIFT) 251 252 /*! @name SOC_INTEGRATOR - FLL_CTRL configuration 2 register */ 253 #define FLL_CTRL_INTEGRATOR_FRACT_PART_MASK (0xFFC0U) 254 #define FLL_CTRL_INTEGRATOR_FRACT_PART_SHIFT (6U) 255 #define FLL_CTRL_INTEGRATOR_FRACT_PART(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_INTEGRATOR_FRACT_PART_SHIFT)) & FLL_CTRL_INTEGRATOR_FRACT_PART_MASK) 256 #define READ_FLL_CTRL_INTEGRATOR_FRACT_PART(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_INTEGRATOR_FRACT_PART_MASK)) >> FLL_CTRL_INTEGRATOR_FRACT_PART_SHIFT) 257 258 #define FLL_CTRL_INTEGRATOR_INT_PART_MASK (0x3FF0000U) 259 #define FLL_CTRL_INTEGRATOR_INT_PART_SHIFT (16U) 260 #define FLL_CTRL_INTEGRATOR_INT_PART(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_INTEGRATOR_INT_PART_SHIFT)) & FLL_CTRL_INTEGRATOR_INT_PART_MASK) 261 #define READ_FLL_CTRL_INTEGRATOR_INT_PART(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_INTEGRATOR_INT_PART_MASK)) >> FLL_CTRL_INTEGRATOR_INT_PART_SHIFT) 262 263 /*! @name FLL_CONVERGE - FLL_CTRL configuration 2 register */ 264 #define FLL_CTRL_SOC_FLL_CONV_MASK (0x1U) 265 #define FLL_CTRL_SOC_FLL_CONV_SHIFT (0U) 266 #define FLL_CTRL_SOC_FLL_CONV(x) (((uint32_t)(((uint32_t)(x)) /*<< FLL_CTRL_SOC_FLL_CONV_SHIFT */)) & FLL_CTRL_SOC_FLL_CONV_MASK) 267 #define READ_FLL_CTRL_SOC_FLL_CONV(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_SOC_FLL_CONV_MASK)) /*>> FLL_CTRL_SOC_FLL_CONV_SHIFT*/) 268 269 #define FLL_CTRL_CLUSTER_FLL_CONV_MASK (0x2U) 270 #define FLL_CTRL_CLUSTER_FLL_CONV_SHIFT (1U) 271 #define FLL_CTRL_CLUSTER_FLL_CONV(x) (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CLUSTER_FLL_CONV_SHIFT)) & FLL_CTRL_CLUSTER_FLL_CONV_MASK) 272 #define READ_FLL_CTRL_CLUSTER_FLL_CONV(x) (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CLUSTER_FLL_CONV_MASK)) >> FLL_CTRL_CLUSTER_FLL_CONV_SHIFT) 273 274 275 /*! 276 * @} 277 */ /* end of group FLL_CTRL_Register_Masks */ 278 279 /* The number of FLL */ 280 #define FLL_NUM ARCHI_NB_FLL 281 /* The FLL reference frequency*/ 282 #define FLL_REF_CLK ARCHI_REF_CLOCK 283 284 285 /* FLL_CTRL - Peripheral instance base addresses */ 286 /** Peripheral FLL_CTRL base address */ 287 #define FLL_CTRL_BASE (SOC_PERIPHERALS_ADDR) 288 /** Peripheral FLL_CTRL base pointer */ 289 #define FLL_CTRL ((FLL_CTRL_Type *)FLL_CTRL_BASE) 290 /** Array initializer of FLL_CTRL base addresses */ 291 #define FLL_CTRL_BASE_ADDRS { FLL_CTRL_BASE } 292 /** Array initializer of FLL_CTRL base pointers */ 293 #define FLL_CTRL_BASE_PTRS { FLL_CTRL } 294 295 /*! 296 * @} 297 */ /* end of group FLL_CTRL_Peripheral_Access_Layer */ 298 299 300 /* ---------------------------------------------------------------------------- 301 -- GPIO Peripheral Access Layer 302 ---------------------------------------------------------------------------- */ 303 #include "hal_gpio_periph.h" 304 #define gpio(id) (((gpio_t *) GPIO_ADDR) + id) 305 306 307 308 /* ---------------------------------------------------------------------------- 309 -- UDMA Peripheral Access Layer 310 ---------------------------------------------------------------------------- */ 311 312 /*! 313 * @addtogroup UDMA_Peripheral_Access_Layer UDMA Peripheral Access Layer 314 * @{ 315 */ 316 317 /** UDMA - General Register Layout Typedef */ 318 typedef struct { 319 __IO uint32_t RX_SADDR; /**< RX UDMA buffer transfer address register, offset: 0x0 */ 320 __IO uint32_t RX_SIZE; /**< RX UDMA buffer transfer size register, offset: 0x4 */ 321 __IO uint32_t RX_CFG; /**< RX UDMA transfer configuration register, offset: 0x8 */ 322 __IO uint32_t RX_INITCFG; /**< Reserved, offset: 0xC */ 323 __IO uint32_t TX_SADDR; /**< TX UDMA buffer transfer address register, offset: 0x10 */ 324 __IO uint32_t TX_SIZE; /**< TX UDMA buffer transfer size register, offset: 0x14 */ 325 __IO uint32_t TX_CFG; /**< TX UDMA transfer configuration register, offset: 0x18 */ 326 __IO uint32_t TX_INITCFG; /**< Reserved, offset: 0x1C */ 327 328 } UDMA_Type; 329 330 #include "hal_udma_core_periph.h" 331 /* ---------------------------------------------------------------------------- 332 -- UDMA Register Masks 333 ---------------------------------------------------------------------------- */ 334 335 /*! 336 * @addtogroup UDMA_Register_Masks UDMA Register Masks 337 * @{ 338 */ 339 /*! @name RX_SADDR - RX TX UDMA buffer transfer address register */ 340 #define UDMA_SADDR_ADDR_MASK (0xFFFFU) 341 #define UDMA_SADDR_ADDR_SHIFT (0U) 342 #define UDMA_SADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) /*<< UDMA_SADDR_ADDR_SHIFT*/)) & UDMA_SADDR_ADDR_MASK) 343 344 /*! @name RX_SIZE - RX TX UDMA buffer transfer size register */ 345 #define UDMA_SIZE_SIZE_MASK (0x1FFFFU) 346 #define UDMA_SIZE_SIZE_SHIFT (0U) 347 #define UDMA_SIZE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << UDMA_SIZE_SIZE_SHIFT)) & UDMA_SIZE_SIZE_MASK) 348 349 350 /*! @name RX_CFG - RX TX UDMA transfer configuration register */ 351 #define UDMA_CFG_CONTINOUS_MASK (0x1U) 352 #define UDMA_CFG_CONTINOUS_SHIFT (0U) 353 #define UDMA_CFG_CONTINOUS(x) (((uint32_t)(((uint32_t)(x)) /*<< UDMA_CFG_CONTINOUS_SHIFT*/)) & UDMA_CFG_CONTINOUS_MASK) 354 #define UDMA_CFG_DATA_SIZE_MASK (0x6U) 355 #define UDMA_CFG_DATA_SIZE_SHIFT (1U) 356 #define UDMA_CFG_DATA_SIZE(x) (((uint32_t)(((uint32_t)(x)) << UDMA_CFG_DATA_SIZE_SHIFT)) & UDMA_CFG_DATA_SIZE_MASK) 357 #define UDMA_CFG_EN_MASK (0x10U) 358 #define UDMA_CFG_EN_SHIFT (4U) 359 #define UDMA_CFG_EN(x) (((uint32_t)(((uint32_t)(x)) << UDMA_CFG_EN_SHIFT)) & UDMA_CFG_EN_MASK) 360 #define UDMA_CFG_PENDING_MASK (0x20U) 361 #define UDMA_CFG_PENDING_SHIFT (5U) 362 #define UDMA_CFG_PENDING(x) (((uint32_t)(((uint32_t)(x)) << UDMA_CFG_PENDING_SHIFT)) & UDMA_CFG_PENDING_MASK) 363 #define UDMA_CFG_CLR_MASK (0x20U) 364 #define UDMA_CFG_CLR_SHIFT (5U) 365 #define UDMA_CFG_CLR(x) (((uint32_t)(((uint32_t)(x)) << UDMA_CFG_CLR_SHIFT)) & UDMA_CFG_CLR_MASK) 366 367 /*! 368 * @} 369 */ /* end of group UDMA_Register_Masks */ 370 371 372 /* UDMA - Peripheral instance base addresses */ 373 /** Peripheral UDMA base address 0x1A102080 */ 374 #define UDMA_BASE UDMA_PERIPH_BASE_ADDR 375 /** Peripheral UDMA events number */ 376 /* TODO: check those */ 377 #define UDMA_EVENTS_NUM 19 378 /** Peripheral UDMA channel number */ 379 #define UDMA_CHANNEL_NUM 10 380 381 /*! 382 * @} 383 */ /* end of group UDMA_Peripheral_Access_Layer */ 384 385 386 387 388 /* ---------------------------------------------------------------------------- 389 -- UDMA Global Configuration Access Layer 390 ---------------------------------------------------------------------------- */ 391 392 /*! 393 * @addtogroup UDMA_GC_Peripheral_Access_Layer UDMA_GC Peripheral Access Layer 394 * @{ 395 */ 396 397 /** UDMA Global configuration - Register Layout Typedef */ 398 typedef struct { 399 __IO uint32_t CG; /**< UDMA_GC clock gating register, offset: 0x0 */ 400 __IO uint32_t EVTIN; /**< UDMA_GC input event register, offset: 0x04 */ 401 } UDMA_GC_Type; 402 403 /* ---------------------------------------------------------------------------- 404 -- UDMA_GC Register Masks 405 ---------------------------------------------------------------------------- */ 406 /*! 407 * @addtogroup UDMA_GC_Register_Masks UDMA_GC Register Masks 408 * @{ 409 */ 410 411 /*! @name UDMA_GC - UDMA event in register, User chooses which events can come to UDMA as reference events, support up to 4 choices */ 412 #define UDMA_GC_EVTIN_CHOICE0_MASK (0xFFU) 413 #define UDMA_GC_EVTIN_CHOICE0_SHIFT (0U) 414 #define UDMA_GC_EVTIN_CHOICE0(x) (((uint32_t)(((uint32_t)(x)) << UDMA_GC_EVTIN_CHOICE0_SHIFT)) & UDMA_GC_EVTIN_CHOICE0_MASK) 415 416 #define UDMA_GC_EVTIN_CHOICE1_MASK (0xFF00U) 417 #define UDMA_GC_EVTIN_CHOICE1_SHIFT (8U) 418 #define UDMA_GC_EVTIN_CHOICE1(x) (((uint32_t)(((uint32_t)(x)) << UDMA_GC_EVTIN_CHOICE1_SHIFT)) & UDMA_GC_EVTIN_CHOICE1_MASK) 419 420 #define UDMA_GC_EVTIN_CHOICE2_MASK (0xFF0000U) 421 #define UDMA_GC_EVTIN_CHOICE2_SHIFT (16U) 422 #define UDMA_GC_EVTIN_CHOICE2(x) (((uint32_t)(((uint32_t)(x)) << UDMA_GC_EVTIN_CHOICE2_SHIFT)) & UDMA_GC_EVTIN_CHOICE2_MASK) 423 424 #define UDMA_GC_EVTIN_CHOICE3_MASK (0xFF000000) 425 #define UDMA_GC_EVTIN_CHOICE3_SHIFT (24U) 426 #define UDMA_GC_EVTIN_CHOICE3(x) (((uint32_t)(((uint32_t)(x)) << UDMA_GC_EVTIN_CHOICE3_SHIFT)) & UDMA_GC_EVTIN_CHOICE3_MASK) 427 428 #define UDMA_GC_EVTIN_MASK(evt_in) (evt_in&0xFF) 429 #define UDMA_GC_EVTIN_SHIFT_ID(id) (id*8) 430 431 /*! 432 * @} 433 */ /* end of group UDMA_GC_Register_Masks */ 434 435 436 /* UDMA Global configuration - instance base addresses */ 437 /** Global configuration UDMA base address */ 438 #define UDMA_GC_BASE (UDMA_CTRL_ADDR) 439 #define UDMA_GC ((UDMA_GC_Type *)UDMA_GC_BASE) 440 441 /*! 442 * @} 443 */ /* end of group UDMA_GC_Peripheral_Access_Layer */ 444 445 446 /* ---------------------------------------------------------------------------- 447 -- SPIM Peripheral Access Layer 448 ---------------------------------------------------------------------------- */ 449 #include "hal_spi_periph.h" 450 451 452 /* ---------------------------------------------------------------------------- 453 -- HYPERBUS Peripheral Access Layer 454 ---------------------------------------------------------------------------- */ 455 #include "core-v-mcu-memory-map.h" 456 #include "core-v-mcu-events.h" 457 /* #include "periph/hyper_periph.h" */ 458 #define hyperbus(id) ((hyperbus_t *) UDMA_HYPER(id)) 459 460 461 /* ---------------------------------------------------------------------------- 462 -- UART Peripheral Access Layer 463 ---------------------------------------------------------------------------- */ 464 #include "hal_uart_periph.h" 465 #define uart(id) ((uart_t *) UDMA_UART(id)) 466 467 468 /* ---------------------------------------------------------------------------- 469 -- I2C Peripheral Access Layer 470 ---------------------------------------------------------------------------- */ 471 #include "hal_i2c_periph.h" 472 #define i2c(id) ((i2c_t *) UDMA_I2C(id)) 473 474 475 /* ---------------------------------------------------------------------------- 476 -- DMACPY Peripheral Access Layer 477 ---------------------------------------------------------------------------- */ 478 /* #include "periph/dmacpy_periph.h" */ 479 #define dmacpy(id) ((dmacpy_t *) UDMA_DMACPY(id)) 480 481 482 /* ---------------------------------------------------------------------------- 483 -- I2S Peripheral Access Layer 484 ---------------------------------------------------------------------------- */ 485 //#include "periph/i2s_periph.h" 486 #define i2s(id) ((i2s_t *) UDMA_I2S(id)) 487 488 489 /* ---------------------------------------------------------------------------- 490 -- CPI Peripheral 491 ---------------------------------------------------------------------------- */ 492 /* #include "periph/cpi_periph.h" */ 493 #define cpi(id) ((cpi_t *) UDMA_CPI(id)) 494 495 496 497 /* ---------------------------------------------------------------------------- 498 -- SOC_CTRL Peripheral 499 ---------------------------------------------------------------------------- */ 500 #include "hal_soc_ctrl_periph.h" 501 #define soc_ctrl ((soc_ctrl_t *) APB_SOC_CTRL_ADDR) 502 503 /* TODO: Remove this instance. */ 504 /* SOC_CTRL - Peripheral instance base addresses */ 505 /** Peripheral SOC_CTRL base address */ 506 #define SOC_CTRL_BASE (SOC_PERIPHERALS_ADDR + 0x4000u) 507 508 509 /* ---------------------------------------------------------------------------- 510 -- PMU CTRL Access Layer 511 ---------------------------------------------------------------------------- */ 512 513 /*! 514 * @addtogroup PMU_CTRL_Peripheral_Access_Layer PMU_CTRL Peripheral Access Layer 515 * @{ 516 */ 517 518 /** PMU - General Register Layout Typedef */ 519 typedef struct { 520 __IO uint32_t RAR_DCDC; /**< PMU CTRL control register, offset: 0x000 */ 521 __IO uint32_t SLEEP_CTRL; /**< PMU CTRL sleep control register, offset: 0x004 */ 522 __IO uint32_t FORCE; /**< PMU CTRL register, offset: 0x008 */ 523 524 } PMU_CTRL_Type; 525 526 527 /* ---------------------------------------------------------------------------- 528 -- PMU_CTRL Register Masks 529 ---------------------------------------------------------------------------- */ 530 531 /*! 532 * @addtogroup PMU_CTRL_Register_Masks PMU_CTRL Register Masks 533 * @{ 534 */ 535 /*! @name RAR_DCDC - PMU control register */ 536 #define PMU_CTRL_RAR_DCDC_NV_MASK (0x1FU) 537 #define PMU_CTRL_RAR_DCDC_NV_SHIFT (0U) 538 #define PMU_CTRL_RAR_DCDC_NV(x) (((uint32_t)(((uint32_t)(x)) /* << PMU_CTRL_RAR_DCDC_NV_SHIFT*/)) & PMU_CTRL_RAR_DCDC_NV_MASK) 539 #define READ_PMU_CTRL_RAR_DCDC_NV(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_RAR_DCDC_NV_MASK)) /*>> PMU_CTRL_RAR_DCDC_NV_SHIFT*/) 540 #define PMU_CTRL_RAR_DCDC_MV_MASK (0x1F00U) 541 #define PMU_CTRL_RAR_DCDC_MV_SHIFT (8U) 542 #define PMU_CTRL_RAR_DCDC_MV(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_RAR_DCDC_MV_SHIFT)) & PMU_CTRL_RAR_DCDC_MV_MASK) 543 #define READ_PMU_CTRL_RAR_DCDC_MV(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_RAR_DCDC_MV_MASK)) >> PMU_CTRL_RAR_DCDC_MV_SHIFT) 544 #define PMU_CTRL_RAR_DCDC_LV_MASK (0x1F0000U) 545 #define PMU_CTRL_RAR_DCDC_LV_SHIFT (16U) 546 #define PMU_CTRL_RAR_DCDC_LV(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_RAR_DCDC_LV_SHIFT)) & PMU_CTRL_RAR_DCDC_LV_MASK) 547 #define READ_PMU_CTRL_RAR_DCDC_LV(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_RAR_DCDC_LV_MASK)) >> PMU_CTRL_RAR_DCDC_LV_SHIFT) 548 #define PMU_CTRL_RAR_DCDC_RV_MASK (0x1F000000U) 549 #define PMU_CTRL_RAR_DCDC_RV_SHIFT (24U) 550 #define PMU_CTRL_RAR_DCDC_RV(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_RAR_DCDC_RV_SHIFT)) & PMU_CTRL_RAR_DCDC_RV_MASK) 551 #define READ_PMU_CTRL_RAR_DCDC_RV(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_RAR_DCDC_RV_MASK)) >> PMU_CTRL_RAR_DCDC_RV_SHIFT) 552 553 /*! @name SLEEP_CTRL - PMU control register */ 554 #define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK (0xFU) 555 #define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT (0U) 556 #define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x) (((uint32_t)(((uint32_t)(x)) /* << PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT*/)) & PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK) 557 #define READ_PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK)) /*>> PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT*/) 558 559 #define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK (0x10U) 560 #define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT (4U) 561 #define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT)) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK) 562 #define READ_PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK)) >> PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT) 563 564 #define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_MASK (0x20U) 565 #define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_SHIFT (5U) 566 #define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_SHIFT)) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_MASK) 567 #define READ_PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_MASK)) >> PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_SHIFT) 568 569 #define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_MASK (0x7C0U) 570 #define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_SHIFT (6U) 571 #define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_SHIFT)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_MASK) 572 #define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_MASK)) >> PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_SHIFT) 573 574 #define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_MASK (0x1800U) 575 #define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_SHIFT (11U) 576 #define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_SHIFT)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_MASK) 577 #define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_MASK)) >> PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_SHIFT) 578 579 #define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_MASK (0x2000U) 580 #define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_SHIFT (13U) 581 #define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_SHIFT)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_MASK) 582 #define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_MASK)) >> PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_SHIFT) 583 584 #define PMU_CTRL_SLEEP_CTRL_WAKEUP_MASK (0xC000U) 585 #define PMU_CTRL_SLEEP_CTRL_WAKEUP_SHIFT (14U) 586 #define PMU_CTRL_SLEEP_CTRL_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_WAKEUP_SHIFT)) & PMU_CTRL_SLEEP_CTRL_WAKEUP_MASK) 587 #define READ_PMU_CTRL_SLEEP_CTRL_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_WAKEUP_MASK)) >> PMU_CTRL_SLEEP_CTRL_WAKEUP_SHIFT) 588 589 #define PMU_CTRL_SLEEP_CTRL_BOOT_L2_MASK (0x10000U) 590 #define PMU_CTRL_SLEEP_CTRL_BOOT_L2_SHIFT (16U) 591 #define PMU_CTRL_SLEEP_CTRL_BOOT_L2(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_BOOT_L2_SHIFT)) & PMU_CTRL_SLEEP_CTRL_BOOT_L2_MASK) 592 #define READ_PMU_CTRL_SLEEP_CTRL_BOOT_L2(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_BOOT_L2_MASK)) >> PMU_CTRL_SLEEP_CTRL_BOOT_L2_SHIFT) 593 594 #define PMU_CTRL_SLEEP_CTRL_REBOOT_MASK (0xC0000U) 595 #define PMU_CTRL_SLEEP_CTRL_REBOOT_SHIFT (18U) 596 #define PMU_CTRL_SLEEP_CTRL_REBOOT(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_REBOOT_SHIFT)) & PMU_CTRL_SLEEP_CTRL_REBOOT_MASK) 597 #define READ_PMU_CTRL_SLEEP_CTRL_REBOOT(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_REBOOT_MASK)) >> PMU_CTRL_SLEEP_CTRL_REBOOT_SHIFT) 598 599 #define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_MASK (0x100000U) 600 #define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_SHIFT (20U) 601 #define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_SHIFT)) & PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_MASK) 602 #define READ_PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_MASK)) >> PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_SHIFT) 603 604 /*! @name FORCE - PMU control register */ 605 #define PMU_CTRL_FORCE_MEM_RET_MASK (0xFU) 606 #define PMU_CTRL_FORCE_MEM_RET_SHIFT (0U) 607 #define PMU_CTRL_FORCE_MEM_RET(x) (((uint32_t)(((uint32_t)(x)) /* << PMU_CTRL_FORCE_MEM_RET_SHIFT*/)) & PMU_CTRL_FORCE_MEM_RET_MASK) 608 609 #define PMU_CTRL_FORCE_MEM_PWD_MASK (0xF0U) 610 #define PMU_CTRL_FORCE_MEM_PWD_SHIFT (4U) 611 #define PMU_CTRL_FORCE_MEM_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_FORCE_MEM_PWD_SHIFT)) & PMU_CTRL_FORCE_MEM_PWD_MASK) 612 613 #define PMU_CTRL_FORCE_FLL_CLUSTER_RET_MASK (0x100U) 614 #define PMU_CTRL_FORCE_FLL_CLUSTER_RET_SHIFT (8U) 615 #define PMU_CTRL_FORCE_FLL_CLUSTER_RET(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_FORCE_FLL_CLUSTER_RET_SHIFT)) & PMU_CTRL_FORCE_FLL_CLUSTER_RET_MASK) 616 617 #define PMU_CTRL_FORCE_FLL_CLUSTER_PWD_MASK (0x200U) 618 #define PMU_CTRL_FORCE_FLL_CLUSTER_PWD_SHIFT (9U) 619 #define PMU_CTRL_FORCE_FLL_CLUSTER_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_FORCE_FLL_CLUSTER_PWD_SHIFT)) & PMU_CTRL_FORCE_FLL_CLUSTER_PWD_MASK) 620 621 /*! 622 * @} 623 */ /* end of group PMU_CTRL_Register_Masks */ 624 625 626 /* PMU CTRL- Peripheral instance base addresses */ 627 /** Peripheral PMU CTRL base address */ 628 #define PMU_CTRL_BASE (SOC_CTRL_BASE + 0x0100u) 629 /** Peripheral PMU_CTRL0 base pointer */ 630 #define PMU_CTRL ((PMU_CTRL_Type *)PMU_CTRL_BASE) 631 /** Array initializer of PMU_CTRL base addresses */ 632 #define PMU_CTRL_BASE_ADDRS { PMU_CTRL_BASE } 633 /** Array initializer of PMU_CTRL base pointers */ 634 #define PMU_CTRL_BASE_PTRS { PMU_CTRL } 635 636 /*! 637 * @} 638 */ /* end of group PMU_CTRL_Peripheral_Access_Layer */ 639 640 641 642 /* ---------------------------------------------------------------------------- 643 -- PORT Peripheral Access Layer 644 ---------------------------------------------------------------------------- */ 645 646 /*! 647 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 648 * @{ 649 */ 650 651 /** PORT - Register Layout Typedef */ 652 typedef struct { 653 __IO uint32_t PADFUN[4]; /**< PORT pad function register 0, offset: 0x000 */ 654 __IO uint32_t SLEEP_PADCFG[4]; /**< PORT sleep pad configuration register 0, offset: 0x010 */ 655 __IO uint32_t PAD_SLEEP; /**< PORT pad sleep register, offset: 0x020 */ 656 __IO uint32_t _reserved0[7]; /**< reserved, offset: 0x010 */ 657 __IO uint32_t PADCFG[16]; /**< PORT pad configuration register 0, offset: 0x040 */ 658 659 } PORT_Type; 660 661 /* ---------------------------------------------------------------------------- 662 -- PORT Register Masks 663 ---------------------------------------------------------------------------- */ 664 665 /*! 666 * @addtogroup PORT_Register_Masks GPIO Register Masks 667 * @{ 668 */ 669 #define GPIO_NUM 32 670 671 /*! @name PADFUN - GPIO pad mux registers */ 672 #define PORT_PADFUN_MUX_MASK (0x3U) 673 #define PORT_PADFUN_MUX_SHIFT (0U) 674 #define PORT_PADFUN_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PADFUN_MUX_SHIFT)) & PORT_PADFUN_MUX_MASK) 675 676 /*! @name PADCFG - GPIO pad configuration registers */ 677 #define PORT_PADCFG_PULL_EN_MASK (0x1U) 678 #define PORT_PADCFG_PULL_EN_SHIFT (0U) 679 #define PORT_PADCFG_PULL_EN(x) (((uint32_t)(((uint32_t)(x)) << PORT_PADCFG_PULL_EN_SHIFT)) & PORT_PADCFG_PULL_EN_MASK) 680 #define PORT_PADCFG_DRIVE_STRENGTH_MASK (0x2U) 681 #define PORT_PADCFG_DRIVE_STRENGTH_SHIFT (1U) 682 #define PORT_PADCFG_DRIVE_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << PORT_PADCFG_DRIVE_STRENGTH_SHIFT)) & PORT_PADCFG_DRIVE_STRENGTH_MASK) 683 684 /*! 685 * @} 686 */ /* end of group PORT_Register_Masks */ 687 688 689 /* PORT - Peripheral instance base addresses */ 690 /** Peripheral PORTA base address */ 691 #define PORTA_BASE (SOC_CTRL_BASE + 0x0140u) 692 /** Peripheral PORTA base pointer */ 693 #define PORTA ((PORT_Type *)PORTA_BASE) 694 /** Array initializer of PORT base addresses */ 695 #define PORT_BASE_ADDRS { PORTA_BASE } 696 /** Array initializer of PORT base pointers */ 697 #define PORT_BASE_PTRS { PORTA } 698 699 /*! 700 * @} 701 */ /* end of group PORT_Access_Layer */ 702 703 704 705 /* ---------------------------------------------------------------------------- 706 -- IO POWER DOMAINS ISOLATION Peripheral Access Layer 707 ---------------------------------------------------------------------------- */ 708 709 /*! 710 * @addtogroup IO_ISO_Peripheral_Access_Layer IO_ISO Peripheral Access Layer 711 * @{ 712 */ 713 714 /** IO_ISO - Register Layout Typedef */ 715 typedef struct { 716 __IO uint32_t GPIO_ISO; /**< IO_ISO GPIO power domains isolation, offset: 0x000 */ 717 __IO uint32_t CAM_ISO; /**< IO_ISO Cemera power domains isolation, offset: 0x004 */ 718 __IO uint32_t LVDS_ISO; /**< IO_ISO LVDS power domains isolation, offset: 0x008 */ 719 720 } IO_ISO_Type; 721 722 /* ---------------------------------------------------------------------------- 723 -- IO_ISO Register Masks 724 ---------------------------------------------------------------------------- */ 725 726 /*! 727 * @addtogroup IO_ISO_Register_Masks GPIO Register Masks 728 * @{ 729 */ 730 #define IO_ISO_GPIO_ISO_MASK (0x1U) 731 #define IO_ISO_GPIO_ISO_SHIFT (0U) 732 #define IO_ISO_GPIO_ISO(x) (((uint32_t)(((uint32_t)(x)) /* << IO_ISO_GPIO_ISO_SHIFT */)) & IO_ISO_GPIO_ISO_MASK) 733 734 #define IO_ISO_CAM_ISO_MASK (0x1U) 735 #define IO_ISO_CAM_ISO_SHIFT (0U) 736 #define IO_ISO_CAM_ISO(x) (((uint32_t)(((uint32_t)(x)) /* << IO_ISO_CAM_ISO_SHIFT */)) & IO_ISO_CAM_ISO_MASK) 737 738 #define IO_ISO_LVDS_ISO_MASK (0x1U) 739 #define IO_ISO_LVDS_ISO_SHIFT (0U) 740 #define IO_ISO_LVDS_ISO(x) (((uint32_t)(((uint32_t)(x)) /* << IO_ISO_LVDS_ISO_SHIFT */)) & IO_ISO_LVDS_ISO_MASK) 741 742 743 /*! 744 * @} 745 */ /* end of group IO_ISO_Register_Masks */ 746 747 748 /* IO_ISO - Peripheral instance base addresses */ 749 /** Peripheral IO_ISO base address */ 750 #define IO_ISO_BASE (SOC_CTRL_BASE + 0x01C0u) 751 /** Peripheral IO_ISO base pointer */ 752 #define IO_ISO ((IO_ISO_Type *)IO_ISO_BASE) 753 /** Array initializer of IO_ISO base addresses */ 754 #define IO_ISO_BASE_ADDRS { IO_ISO_BASE } 755 /** Array initializer of IO_ISO base pointers */ 756 #define IO_ISO_BASE_PTRS { IO_ISO } 757 758 /*! 759 * @} 760 */ /* end of group IO_ISO_Access_Layer */ 761 762 763 /* ---------------------------------------------------------------------------- 764 -- PWM Peripheral 765 ---------------------------------------------------------------------------- */ 766 #include "hal_pwm_periph.h" 767 #include "hal_pwm_ctrl_periph.h" 768 #define pwm(id) ((pwm_t *) (ADV_TIMER_ADDR + (id << 6))) 769 #define pwm_ctrl ((pwm_ctrl_t *) (ADV_TIMER_ADDR + 0x100)) 770 771 772 773 /* ---------------------------------------------------------------------------- 774 -- SOCEU (SOC EVENT UNIT) Peripheral Access Layer 775 ---------------------------------------------------------------------------- */ 776 777 /*! 778 * @addtogroup SOCEU_Peripheral_Access_Layer SOCEU Peripheral Access Layer 779 * @{ 780 */ 781 782 /** SOCEU - Register Layout Typedef */ 783 typedef struct { 784 __IO uint32_t EVENT; /**< SOCEU event register, offset: 0x00 */ 785 __IO uint32_t FC_MASK0; /**< SOCEU fc mask 0 register, offset: 0x04 */ 786 __IO uint32_t FC_MASK1; /**< SOCEU fc mask 1 register, offset: 0x08 */ 787 __IO uint32_t FC_MASK2; /**< SOCEU fc mask 2 register, offset: 0x0c */ 788 __IO uint32_t FC_MASK3; /**< SOCEU fc mask 3 register, offset: 0x10 */ 789 __IO uint32_t FC_MASK4; /**< SOCEU fc mask 4 register, offset: 0x14 */ 790 __IO uint32_t FC_MASK5; /**< SOCEU fc mask 5 register, offset: 0x18 */ 791 __IO uint32_t FC_MASK6; /**< SOCEU fc mask 6 register, offset: 0x1c */ 792 __IO uint32_t FC_MASK7; /**< SOCEU fc mask 7 register, offset: 0x20 */ 793 __IO uint32_t CL_MASK0; /**< SOCEU cluster mask 0 register, offset: 0x24 */ 794 __IO uint32_t CL_MASK1; /**< SOCEU cluster mask 1 register, offset: 0x28 */ 795 __IO uint32_t CL_MASK2; /**< SOCEU cluster mask 2 register, offset: 0x2C */ 796 __IO uint32_t CL_MASK3; /**< SOCEU cluster mask 3 register, offset: 0x30 */ 797 __IO uint32_t CL_MASK4; /**< SOCEU cluster mask 4 register, offset: 0x34 */ 798 __IO uint32_t CL_MASK5; /**< SOCEU cluster mask 5 register, offset: 0x38 */ 799 __IO uint32_t CL_MASK6; /**< SOCEU cluster mask 6 register, offset: 0x3C */ 800 __IO uint32_t CL_MASK7; /**< SOCEU cluster mask 7 register, offset: 0x40 */ 801 __IO uint32_t PR_MASK0; /**< SOCEU propagate mask MSB register, offset: 0x44 */ 802 __IO uint32_t PR_MASK1; /**< SOCEU propagate mask MSB register, offset: 0x48 */ 803 __IO uint32_t PR_MASK2; /**< SOCEU propagate mask MSB register, offset: 0x4c */ 804 __IO uint32_t PR_MASK3; /**< SOCEU propagate mask MSB register, offset: 0x50 */ 805 __IO uint32_t PR_MASK4; /**< SOCEU propagate mask MSB register, offset: 0x54 */ 806 __IO uint32_t PR_MASK5; /**< SOCEU propagate mask MSB register, offset: 0x58 */ 807 __IO uint32_t PR_MASK6; /**< SOCEU propagate mask MSB register, offset: 0x5c */ 808 __IO uint32_t PR_MASK7; /**< SOCEU propagate mask MSB register, offset: 0x60 */ 809 __IO uint32_t ERR_MASK0; /**< SOCEU error mask MSB register, offset: 0x64 */ 810 __IO uint32_t ERR_MASK1; /**< SOCEU error mask MSB register, offset: 0x68 */ 811 __IO uint32_t ERR_MASK2; /**< SOCEU error mask MSB register, offset: 0x6c */ 812 __IO uint32_t ERR_MASK3; /**< SOCEU error mask MSB register, offset: 0x70 */ 813 __IO uint32_t ERR_MASK4; /**< SOCEU error mask MSB register, offset: 0x74 */ 814 __IO uint32_t ERR_MASK5; /**< SOCEU error mask MSB register, offset: 0x78 */ 815 __IO uint32_t ERR_MASK6; /**< SOCEU error mask MSB register, offset: 0x7c */ 816 __IO uint32_t ERR_MASK7; /**< SOCEU error mask MSB register, offset: 0x80 */ 817 __IO uint32_t TIMER_SEL_HI; /**< SOCEU timer high register, offset: 0x84 */ 818 __IO uint32_t TIMER_SEL_LO; /**< SOCEU timer low register, offset: 0x88 */ 819 } SOCEU_Type; 820 821 #define SOC_EVENT_OFFSET 0x00 822 #define SOC_FC_MASK0_OFFSET 0x04 823 #define SOC_CL_MASK0_OFFSET 0x24 824 #define SOC_PR_MASK0_OFFSET 0x44 825 #define SOC_ERR_MASK0_OFFSET 0x64 826 827 /* ---------------------------------------------------------------------------- 828 -- SOCEU Register Masks 829 ---------------------------------------------------------------------------- */ 830 831 /*! 832 * @addtogroup SOCEU_Register_Masks SOCEU Register Masks 833 * @{ 834 */ 835 /* The SOC events number */ 836 #define SOC_EVENTS_NUM 0x08 837 /*! 838 * @} 839 */ /* end of group SOCEU_Register_Masks */ 840 841 842 /* SOCEU - Peripheral instance base addresses */ 843 /** Peripheral SOCEU base address */ 844 #define SOCEU_BASE SOC_EU_ADDR 845 /** Peripheral SOCEU base pointer */ 846 #define SOCEU ((SOCEU_Type *)SOCEU_BASE) 847 /** Array initializer of SOCEU base addresses */ 848 #define SOCEU_BASE_ADDRS { SOCEU_BASE } 849 /** Array initializer of SOCEU base pointers */ 850 #define SOCEU_BASE_PTRS { SOCEU } 851 852 /*! 853 * @} 854 */ /* end of group SOCEU_Peripheral_Access_Layer */ 855 856 857 858 /* ---------------------------------------------------------------------------- 859 -- SW EVENT TRIGGER Register Address 860 ---------------------------------------------------------------------------- */ 861 862 #define EU_EVT_GETCLUSTERBASE(coreId) (0x00200800u + (coreId << 6)) 863 864 865 /* ---------------------------------------------------------------------------- 866 -- PMU DLC Access Layer 867 ---------------------------------------------------------------------------- */ 868 869 /*! 870 * @addtogroup PMU_DLC_Peripheral_Access_Layer PMU_DLC Peripheral Access_Layer 871 * @{ 872 */ 873 874 /** PMU - General Register Layout Typedef */ 875 typedef struct { 876 __IO uint32_t PCTRL; /**< PMU DLC control register, offset: 0x00 */ 877 __IO uint32_t PRDATA; /**< PMU DLC data register, offset: 0x04 */ 878 __IO uint32_t DLC_SR; /**< PMU DLC register, offset: 0x08 */ 879 __IO uint32_t DLC_IMR; /**< PMU DLC register, offset: 0x0C */ 880 __IO uint32_t DLC_IFR; /**< PMU DLC register, offset: 0x10 */ 881 __IO uint32_t DLC_IOIFR; /**< PMU DLC register, offset: 0x14 */ 882 __IO uint32_t DLC_IDIFR; /**< PMU DLC register, offset: 0x18 */ 883 __IO uint32_t DLC_IMCIFR; /**< PMU DLC register, offset: 0x1C */ 884 885 } PMU_DLC_Type; 886 887 /* ---------------------------------------------------------------------------- 888 -- SOCEU Register Masks 889 ---------------------------------------------------------------------------- */ 890 /*! 891 * @addtogroup PMU_DLC_Register_Masks PMU_DLC Register Masks 892 * @{ 893 */ 894 895 /*! @name PCTRL - PMU DLC PICL control register */ 896 #define PMU_DLC_PCTRL_START_MASK (0x1U) 897 #define PMU_DLC_PCTRL_START_SHIFT (0U) 898 #define PMU_DLC_PCTRL_START(x) (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_PCTRL_START_SHIFT */)) & PMU_DLC_PCTRL_START_MASK) 899 #define PMU_DLC_PCTRL_PADDR_MASK (0x7FFEU) 900 #define PMU_DLC_PCTRL_PADDR_SHIFT (1U) 901 #define PMU_DLC_PCTRL_PADDR(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_PCTRL_PADDR_SHIFT)) & PMU_DLC_PCTRL_PADDR_MASK) 902 #define PMU_DLC_PCTRL_DIR_MASK (0x8000U) 903 #define PMU_DLC_PCTRL_DIR_SHIFT (15U) 904 #define PMU_DLC_PCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_PCTRL_DIR_SHIFT)) & PMU_DLC_PCTRL_DIR_MASK) 905 #define PMU_DLC_PCTRL_PWDATA_MASK (0xFFFF0000U) 906 #define PMU_DLC_PCTRL_PWDATA_SHIFT (16U) 907 #define PMU_DLC_PCTRL_PWDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_PCTRL_PWDATA_SHIFT)) & PMU_DLC_PCTRL_PWDATA_MASK) 908 909 /*! @name PRDATA - PMU DLC PICL data read register */ 910 #define PMU_DLC_PRDATA_PRDATA_MASK (0xFFU) 911 #define PMU_DLC_PRDATA_PRDATA_SHIFT (0U) 912 #define PMU_DLC_PRDATA_PRDATA(x) (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_PRDATA_PRDATA_SHIFT */)) & PMU_DLC_PRDATA_PRDATA_MASK) 913 914 /*! @name SR - PMU DLC DLC Status register */ 915 #define PMU_DLC_SR_PICL_BUSY_MASK (0x1U) 916 #define PMU_DLC_SR_PICL_BUSY_SHIFT (0U) 917 #define PMU_DLC_SR_PICL_BUSY(x) (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_SR_PICL_BUSY_SHIFT */)) & PMU_DLC_SR_PICL_BUSY_MASK) 918 #define PMU_DLC_SR_SCU_BUSY_MASK (0x2U) 919 #define PMU_DLC_SR_SCU_BUSY_SHIFT (1U) 920 #define PMU_DLC_SR_SCU_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_SR_SCU_BUSY_SHIFT)) & PMU_DLC_SR_SCU_BUSY_MASK) 921 922 /*! @name IMR - PMU DLC Interrupt mask register */ 923 #define PMU_DLC_IMR_ICU_OK_MASK_MASK (0x1U) 924 #define PMU_DLC_IMR_ICU_OK_MASK_SHIFT (0U) 925 #define PMU_DLC_IMR_ICU_OK_MASK(x) (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_IMR_ICU_OK_MASK_SHIFT */)) & PMU_DLC_IMR_ICU_OK_MASK_MASK) 926 #define PMU_DLC_IMR_ICU_DELAYED_MASK_MASK (0x2U) 927 #define PMU_DLC_IMR_ICU_DELAYED_MASK_SHIFT (1U) 928 #define PMU_DLC_IMR_ICU_DELAYED_MASK(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IMR_ICU_DELAYED_MASK_SHIFT)) & PMU_DLC_IMR_ICU_DELAYED_MASK_MASK) 929 #define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_MASK (0x4U) 930 #define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_SHIFT (2U) 931 #define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_SHIFT)) & PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_MASK) 932 #define PMU_DLC_IMR_PICL_OK_MASK_MASK (0x8U) 933 #define PMU_DLC_IMR_PICL_OK_MASK_SHIFT (3U) 934 #define PMU_DLC_IMR_PICL_OK_MASK(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IMR_PICL_OK_MASK_SHIFT)) & PMU_DLC_IMR_PICL_OK_MASK_MASK) 935 #define PMU_DLC_IMR_SCU_OK_MASK_MASK (0x10U) 936 #define PMU_DLC_IMR_SCU_OK_MASK_SHIFT (4U) 937 #define PMU_DLC_IMR_SCU_OK_MASK(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IMR_SCU_OK_MASK_SHIFT)) & PMU_DLC_IMR_SCU_OK_MASK_MASK) 938 939 /*! @name IFR - PMU DLC Interrupt flag register */ 940 #define PMU_DLC_IFR_ICU_OK_FLAG_MASK (0x1U) 941 #define PMU_DLC_IFR_ICU_OK_FLAG_SHIFT (0U) 942 #define PMU_DLC_IFR_ICU_OK_FLAG(x) (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_IFR_ICU_OK_FLAG_SHIFT */)) & PMU_DLC_IFR_ICU_OK_FLAG_MASK) 943 #define PMU_DLC_IFR_ICU_DELAYED_FLAG_MASK (0x2U) 944 #define PMU_DLC_IFR_ICU_DELAYED_FLAG_SHIFT (1U) 945 #define PMU_DLC_IFR_ICU_DELAYED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IFR_ICU_DELAYED_FLAG_SHIFT)) & PMU_DLC_IFR_ICU_DELAYED_FLAG_MASK) 946 #define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_MASK (0x4U) 947 #define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_SHIFT (2U) 948 #define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_SHIFT)) & PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_MASK) 949 #define PMU_DLC_IFR_PICL_OK_FLAG_MASK (0x8U) 950 #define PMU_DLC_IFR_PICL_OK_FLAG_SHIFT (3U) 951 #define PMU_DLC_IFR_PICL_OK_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IFR_PICL_OK_FLAG_SHIFT)) & PMU_DLC_IFR_PICL_OK_FLAG_MASK) 952 #define PMU_DLC_IFR_SCU_OK_FLAG_MASK (0x10U) 953 #define PMU_DLC_IFR_SCU_OK_FLAG_SHIFT (4U) 954 #define PMU_DLC_IFR_SCU_OK_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IFR_SCU_OK_FLAG_SHIFT)) & PMU_DLC_IFR_SCU_OK_FLAG_MASK) 955 956 /*! @name IOIFR - PMU DLC icu_ok interrupt flag register */ 957 #define PMU_DLC_IOIFR_ICU_OK_FLAG_MASK (0xFFFFFFFEU) 958 #define PMU_DLC_IOIFR_ICU_OK_FLAG_SHIFT (1U) 959 #define PMU_DLC_IOIFR_ICU_OK_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IOIFR_ICU_OK_FLAG_SHIFT)) & PMU_DLC_IOIFR_ICU_OK_FLAG_MASK) 960 961 /*! @name IDIFR - PMU DLC icu_delayed interrupt flag register */ 962 #define PMU_DLC_IDIFR_ICU_DELAYED_FLAG_MASK (0xFFFFFFFEU) 963 #define PMU_DLC_IDIFR_ICU_DELAYED_FLAG_SHIFT (1U) 964 #define PMU_DLC_IDIFR_ICU_DELAYED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IDIFR_ICU_DELAYED_FLAG_SHIFT)) & PMU_DLC_IDIFR_ICU_DELAYED_FLAG_MASK) 965 966 /*! @name IMCIFR - PMU DLC icu_mode changed interrupt flag register */ 967 #define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_MASK (0xFFFFFFFEU) 968 #define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_SHIFT (1U) 969 #define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_SHIFT)) & PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_MASK) 970 971 /*! @name PCTRL_PADDR The address to write in the DLC_PADDR register is CHIP_SEL_ADDR[4:0] concatenated with REG_ADDR[4:0]. */ 972 #define PMU_DLC_PICL_REG_ADDR_MASK (0x1FU) 973 #define PMU_DLC_PICL_REG_ADDR_SHIFT (0U) 974 #define PMU_DLC_PICL_REG_ADDR(x) (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_PICL_REG_ADDR_SHIFT */)) & PMU_DLC_PICL_REG_ADDR_MASK) 975 #define PMU_DLC_PICL_CHIP_SEL_ADDR_MASK (0x3E0U) 976 #define PMU_DLC_PICL_CHIP_SEL_ADDR_SHIFT (5U) 977 #define PMU_DLC_PICL_CHIP_SEL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PMU_DLC_PICL_CHIP_SEL_ADDR_SHIFT)) & PMU_DLC_PICL_CHIP_SEL_ADDR_MASK) 978 979 /* CHIP_SEL_ADDR[4:0]*/ 980 #define PICL_WIU_ADDR 0x00 981 #define PICL_ICU_ADDR 0x01 982 983 /* REG_ADDR[4:0]*/ 984 #define WIU_ISPMR_0 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x00)) 985 #define WIU_ISPMR_1 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x01)) 986 #define WIU_IFR_0 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x02)) 987 #define WIU_IFR_1 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x03)) 988 #define WIU_ICR_0 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x04)) 989 #define WIU_ICR_1 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x05)) 990 #define WIU_ICR_2 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x06)) 991 #define WIU_ICR_3 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x07)) 992 #define WIU_ICR_4 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x08)) 993 #define WIU_ICR_5 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x09)) 994 #define WIU_ICR_6 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0A)) 995 #define WIU_ICR_7 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0B)) 996 #define WIU_ICR_8 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0C)) 997 #define WIU_ICR_9 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0D)) 998 #define WIU_ICR_10 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0E)) 999 #define WIU_ICR_11 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0F)) 1000 #define WIU_ICR_12 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x10)) 1001 #define WIU_ICR_13 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x11)) 1002 #define WIU_ICR_14 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x12)) 1003 #define WIU_ICR_15 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x13)) 1004 1005 /* REG_ADDR[4:0]*/ 1006 #define ICU_CR (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x00)) 1007 #define ICU_MR (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x01)) 1008 #define ICU_ISMR (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x02)) 1009 #define ICU_DMR_0 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x03)) 1010 #define ICU_DMA_1 (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x04)) 1011 1012 /*! 1013 * @} 1014 */ /* end of group PMU_DLC_Register_Masks */ 1015 1016 /* PMU DLC- Peripheral instance base addresses */ 1017 /** Peripheral PMU DLC base address */ 1018 #define PMU_DLC_BASE (SOC_PERIPHERALS_ADDR + 0x7000u) 1019 /** Peripheral PMU_DLC base pointer */ 1020 #define PMU_DLC ((PMU_DLC_Type *)PMU_DLC_BASE) 1021 /** Array initializer of PMU_DLC base addresses */ 1022 #define PMU_DLC_BASE_ADDRS { PMU_DLC_BASE } 1023 /** Array initializer of PMU_DLC base pointers */ 1024 #define PMU_DLC_BASE_PTRS { PMU_DLC } 1025 1026 /*! 1027 * @} 1028 */ /* end of group PMU_DLC_Peripheral_Access_Layer */ 1029 1030 1031 /* ---------------------------------------------------------------------------- 1032 -- RTC_APB Peripheral Access Layer 1033 ---------------------------------------------------------------------------- */ 1034 /* #include "periph/rtc_periph.h" */ 1035 /* #define rtc(id) ((rtc_t *) RTC_ADDR) */ 1036 1037 1038 /* ---------------------------------------------------------------------------- 1039 -- EFUSE CTRL Peripheral Access Layer 1040 ---------------------------------------------------------------------------- */ 1041 1042 /*! 1043 * @addtogroup EFUSE_CTRL_Peripheral_Access_Layer EFUSE_CTRL Peripheral Access Layer 1044 * @{ 1045 */ 1046 1047 1048 1049 //#include "periph/efuse_periph.h" 1050 1051 /* EFUSE_CTRL - Peripheral instance base addresses */ 1052 /** Peripheral EFUSE_CTRL base address */ 1053 #define EFUSE_CTRL_BASE (SOC_PERIPHERALS_ADDR + 0x09000u) 1054 /** Peripheral EFUSE_CTRL base pointer */ 1055 #define efuse_ctrl ((efuse_ctrl_t *)EFUSE_CTRL_BASE) 1056 /** Array initializer of EFUSE_CTRL base addresses */ 1057 #define EFUSE_CTRL_BASE_ADDRS { EFUSE_CTRL_BASE } 1058 /** Array initializer of EFUSE_CTRL base pointers */ 1059 #define EFUSE_CTRL_BASE_PTRS { EFUSE_CTRL } 1060 1061 /*! 1062 * @} 1063 */ /* end of group EFUSE_CTRL_Peripheral_Access_Layer */ 1064 1065 1066 /* EFUSE_REGS - Peripheral instance base addresses */ 1067 /** Peripheral EFUSE_REGS base address */ 1068 #define EFUSE_REGS_BASE (SOC_PERIPHERALS_ADDR + 0x09200u) 1069 /** Peripheral EFUSE_REGS base pointer */ 1070 #define efuse_regs ((efuse_regs_t *)EFUSE_REGS_BASE) 1071 #define efuse_regs_array ((int32_t*)EFUSE_REGS_BASE) 1072 /** Array initializer of EFUSE_REGS base addresses */ 1073 #define EFUSE_REGS_BASE_ADDRS { EFUSE_REGS_BASE } 1074 /** Array initializer of EFUSE_REGS base pointers */ 1075 #define EFUSE_REGS_BASE_PTRS { EFUSE_REGS }/*! 1076 * @} 1077 */ /* end of group EFUSE_CTRL_Peripheral_Access_Layer */ 1078 1079 1080 1081 /* ---------------------------------------------------------------------------- 1082 -- EFUSE REG Peripheral Access Layer 1083 ---------------------------------------------------------------------------- */ 1084 1085 /*! 1086 * @addtogroup EFUSE_REGS_Peripheral_Access_Layer EFUSE_REGS Peripheral Access Layer 1087 * @{ 1088 */ 1089 1090 /** EFUSE_REGS - Registers Layout Typedef */ 1091 typedef struct { 1092 __IO uint32_t INFO; /**< EFUSE INFO register, offset: 0x000 */ 1093 __IO uint32_t INFO2; /**< EFUSE_INFO2 register, offset: 0x004 */ 1094 __IO uint32_t AES_KEY[16]; /**< EFUSE_AES_KEY registers, offset: 0x008 */ 1095 __IO uint32_t AES_IV[8]; /**< EFUSE_AES_IV registers, offset: 0x048 */ 1096 __IO uint32_t WAIT_XTAL_DELTA_LSB; /**< EFUSE_WAIT_XTAL_DELTA_LSB register, offset: 0x068 */ 1097 __IO uint32_t WAIT_XTAL_DELTA_MSB; /**< EFUSE_WAIT_XTAL_DELTA_MSB register, offset: 0x06C */ 1098 __IO uint32_t WAIT_XTAL_MIN; /**< EFUSE_WAIT_XTAL_MIN registers, offset: 0x070 */ 1099 __IO uint32_t WAIT_XTAL_MAX; /**< EFUSE_WAIT_XTAL_MAX registers, offset: 0x074 */ 1100 __IO uint32_t HYPER_RDS_DELAY; /**< EFUSE_WAIT_XTAL_MAX registers, offset: 0x078 */ 1101 __IO uint32_t FLL_FREQ; /**< EFUSE_FLL_FREQ registers, offset: 0x07C */ 1102 __IO uint32_t FLL_TOLERANCE; /**< EFUSE_FLL_TOLERANCE registers, offset: 0x080 */ 1103 __IO uint32_t FLL_ASSERT_CYCLE; /**< EFUSE_FLL_ASSERT_CYCLE registers, offset: 0x084 */ 1104 __IO uint32_t _reserved[6]; /**< EFUSE_reserved registers, offset: 0x088 */ 1105 __IO uint32_t USER_REG[88]; /**< EFUSE_USER_REG, offset: 0x0A0 */ 1106 } EFUSE_REGS_Type; 1107 1108 /* ---------------------------------------------------------------------------- 1109 -- EFUSE_REGS Register Masks 1110 ---------------------------------------------------------------------------- */ 1111 1112 /*! 1113 * @addtogroup EFUSE_REGS_Register_Masks EFUSE_REGS Register Masks 1114 * @{ 1115 */ 1116 /*! @name INFO - EFUSE information register */ 1117 #define EFUSE_INFO_PLT_MASK (0x07U) 1118 #define EFUSE_INFO_PLT_SHIFT (0U) 1119 #define EFUSE_INFO_PLT(x) (((uint32_t)(((uint32_t)(x)) /* << EFUSE_INFO_PLT_SHIFT */)) & EFUSE_INFO_PLT_MASK) 1120 1121 #define EFUSE_INFO_BOOT_MASK (0x38U) 1122 #define EFUSE_INFO_BOOT_SHIFT (3U) 1123 #define EFUSE_INFO_BOOT(x) (((uint32_t)(((uint32_t)(x)) << EFUSE_INFO_BOOT_SHIFT)) & EFUSE_INFO_BOOT_MASK) 1124 1125 #define EFUSE_INFO_ENCRYPTED_MASK (0x40U) 1126 #define EFUSE_INFO_ENCRYPTED_SHIFT (6U) 1127 #define EFUSE_INFO_ENCRYPTED(x) (((uint32_t)(((uint32_t)(x)) << EFUSE_INFO_ENCRYPTED_SHIFT)) & EFUSE_INFO_ENCRYPTED_MASK) 1128 1129 #define EFUSE_INFO_WAIT_XTAL_MASK (0x80U) 1130 #define EFUSE_INFO_WAIT_XTAL_SHIFT (7U) 1131 #define EFUSE_INFO_WAIT_XTAL(x) (((uint32_t)(((uint32_t)(x)) << EFUSE_INFO_WAIT_XTAL_SHIFT)) & EFUSE_INFO_WAIT_XTAL_MASK) 1132 1133 1134 /*! 1135 * @} 1136 */ /* end of group EFUSE_REGS_Register_Masks */ 1137 1138 1139 /* EFUSE_REGS - Peripheral instance base addresses */ 1140 /** Peripheral EFUSE_REGS base address */ 1141 #define EFUSE_REGS_BASE (SOC_PERIPHERALS_ADDR + 0x09200u) 1142 /** Peripheral EFUSE_REGS base pointer */ 1143 #define EFUSE_REGS ((EFUSE_REGS_Type *)EFUSE_REGS_BASE) 1144 /** Array initializer of EFUSE_REGS base addresses */ 1145 #define EFUSE_REGS_BASE_ADDRS { EFUSE_REGS_BASE } 1146 /** Array initializer of EFUSE_REGS base pointers */ 1147 #define EFUSE_REGS_BASE_PTRS { EFUSE_REGS } 1148 1149 /*! 1150 * @} 1151 */ /* end of group EFUSE_REGS_Peripheral_Access_Layer */ 1152 1153 1154 1155 /* ---------------------------------------------------------------------------- 1156 -- FC_STDOUT Peripheral Access Layer 1157 ---------------------------------------------------------------------------- */ 1158 1159 /*! 1160 * @addtogroup FC_STDOUT_Peripheral_Access_Layer FC_STDOUT Peripheral Access Layer 1161 * @{ 1162 */ 1163 1164 /** FC_STDOUT - Registers Layout Typedef */ 1165 typedef struct { 1166 __IO uint32_t PUTC[16]; /**< FC_STDOUT INFO register, offset: 0x000 */ 1167 } FC_STDOUT_Type; 1168 1169 /* ---------------------------------------------------------------------------- 1170 -- FC_STDOUT Register Masks 1171 ---------------------------------------------------------------------------- */ 1172 1173 /*! 1174 * @addtogroup FC_STDOUT_Register_Masks FC_STDOUT Register Masks 1175 * @{ 1176 */ 1177 /*! @name INFO - FC_STDOUT information register */ 1178 1179 /*! 1180 * @} 1181 */ /* end of group FC_STDOUT_Register_Masks */ 1182 1183 1184 /* FC_STDOUT - Peripheral instance base addresses */ 1185 /** Peripheral FC_STDOUT base address */ 1186 #define FC_STDOUT_BASE (SOC_PERIPHERALS_ADDR + 0x10000u + (FC_CLUSTER_ID << 7)) 1187 /** Peripheral FC_STDOUT base pointer */ 1188 #define FC_STDOUT ((FC_STDOUT_Type *)FC_STDOUT_BASE) 1189 /** Array initializer of FC_STDOUT base addresses */ 1190 #define FC_STDOUT_BASE_ADDRS { FC_STDOUT_BASE } 1191 /** Array initializer of FC_STDOUT base pointers */ 1192 #define FC_STDOUT_BASE_PTRS { FC_STDOUT } 1193 1194 /*! 1195 * @} 1196 */ /* end of group FC_STDOUT_Peripheral_Access_Layer */ 1197 1198 1199 #ifdef FEATURE_CLUSTER 1200 /* ---------------------------------------------------------------------------- 1201 -- CLUSTER_STDOUT Peripheral Access Layer 1202 ---------------------------------------------------------------------------- */ 1203 1204 /*! 1205 * @addtogroup CLUSTER_STDOUT_Peripheral_Access_Layer CLUSTER_STDOUT Peripheral Access Layer 1206 * @{ 1207 */ 1208 1209 /** CLUSTER_STDOUT - Registers Layout Typedef */ 1210 typedef struct { 1211 __IO uint32_t PUTC[16]; /**< CLUSTER_STDOUT INFO register, offset: 0x000 */ 1212 } CLUSTER_STDOUT_Type; 1213 1214 /* ---------------------------------------------------------------------------- 1215 -- CLUSTER_STDOUT Register Masks 1216 ---------------------------------------------------------------------------- */ 1217 1218 /*! 1219 * @addtogroup CLUSTER_STDOUT_Register_Masks CLUSTER_STDOUT Register Masks 1220 * @{ 1221 */ 1222 /*! @name INFO - CLUSTER_STDOUT information register */ 1223 1224 /*! 1225 * @} 1226 */ /* end of group CLUSTER_STDOUT_Register_Masks */ 1227 1228 1229 /* CLUSTER_STDOUT - Peripheral instance base addresses */ 1230 /** Peripheral CLUSTER_STDOUT base address */ 1231 #define CLUSTER_STDOUT_BASE (SOC_PERIPHERALS_ADDR + 0x10000u) 1232 /** Peripheral CLUSTER_STDOUT base pointer */ 1233 #define CLUSTER_STDOUT ((CLUSTER_STDOUT_Type *)CLUSTER_STDOUT_BASE) 1234 /** Array initializer of CLUSTER_STDOUT base addresses */ 1235 #define CLUSTER_STDOUT_BASE_ADDRS { CLUSTER_STDOUT_BASE } 1236 /** Array initializer of CLUSTER_STDOUT base pointers */ 1237 #define CLUSTER_STDOUT_BASE_PTRS { CLUSTER_STDOUT } 1238 1239 /*! 1240 * @} 1241 */ /* end of group CLUSTER_STDOUT_Peripheral_Access_Layer */ 1242 1243 1244 1245 1246 /* ---------------------------------------------------------------------------- 1247 -- HWCE Peripheral Access Layer 1248 ---------------------------------------------------------------------------- */ 1249 1250 /*! 1251 * @addtogroup HWCE Peripheral_Access_Layer HWCE Peripheral Access Layer 1252 * @{ 1253 */ 1254 1255 /** HWCE - Registers Layout Typedef */ 1256 typedef struct { 1257 __IO uint32_t HWCE_TRIGGER_REG; /**< HWCE Trigger register, offset: 0x00 */ 1258 __IO uint32_t HWCE_ACQUIRE_REG; /**< HWCE Acquire register, offset: 0x04 */ 1259 __IO uint32_t HWCE_FINISHED_REG; /**< HWCE Finished register, offset: 0x08 */ 1260 __IO uint32_t HWCE_STATUS_REG; /**< HWCE Status register, offset: 0x0C */ 1261 __IO uint32_t HWCE_RUNNING_JOB_REG; /**< HWCE Running Job register, offset: 0x10 */ 1262 __IO uint32_t HWCE_SOFT_CLEAR_REG; /**< HWCE Soft_Clear register, offset: 0x14 */ 1263 __IO uint32_t _reserved0[2]; /**< HWCE Non used registers, offser: 0x18 */ 1264 __IO uint32_t HWCE_GEN_CONFIG0_REG; /**< HWCE Gen_Config0 register, offset: 0x20 */ 1265 __IO uint32_t HWCE_GEN_CONFIG1_REG; /**< HWCE Gen_Config1 register, offset: 0x24 */ 1266 __IO uint32_t _reserved1[6]; /**< HWCE unused registers, offset: 0x28 */ 1267 __IO uint32_t HWCE_Y_TRANS_SIZE_REG; /**< HWCE Y_Trans_Size register, offset: 0x40 */ 1268 __IO uint32_t HWCE_Y_LINE_STRIDE_LENGTH_REG; /**< HWCE Y_Line_Stride_Length register, offset: 0x44 */ 1269 __IO uint32_t HWCE_Y_FEAT_STRIDE_LENGTH_REG; /**< HWCE Y_Feat_Stride_Length register, offset: 0x48 */ 1270 __IO uint32_t HWCE_Y_OUT_3_REG; /**< HWCE Y_Out_3 register, offset: 0x4C */ 1271 __IO uint32_t HWCE_Y_OUT_2_REG; /**< HWCE Y_Out_2 register, offset: 0x50 */ 1272 __IO uint32_t HWCE_Y_OUT_1_REG; /**< HWCE Y_Out_1 register, offset: 0x54 */ 1273 __IO uint32_t HWCE_Y_OUT_0_REG; /**< HWCE Y_Out_0 register, offset: 0x58 */ 1274 __IO uint32_t HWCE_Y_IN_3_REG; /**< HWCE Y_In_3 register, offset: 0x5C */ 1275 __IO uint32_t HWCE_Y_IN_2_REG; /**< HWCE Y_In_2 register, offset: 0x60 */ 1276 __IO uint32_t HWCE_Y_IN_1_REG; /**< HWCE Y_In_1 register, offset: 0x64 */ 1277 __IO uint32_t HWCE_Y_IN_0_REG; /**< HWCE Y_In_0 register, offset: 0x68 */ 1278 __IO uint32_t HWCE_X_TRANS_SIZE_REG; /**< HWCE X_Trans_Size register, offset: 0x6C */ 1279 __IO uint32_t HWCE_X_LINE_STRIDE_LENGTH_REG; /**< HWCE X_Line_Stride_Length register, offset: 0x70 */ 1280 __IO uint32_t HWCE_X_FEAT_STRIDE_LENGTH_REG; /**< HWCE X_Feat_Stride_Length register, offset: 0x74 */ 1281 __IO uint32_t HWCE_X_IN_REG; /**< HWCE X_In register, offset: 0x78 */ 1282 __IO uint32_t HWCE_W_REG; /**< HWCE W register, offset: 0x7C */ 1283 __IO uint32_t HWCE_JOB_CONFIG0_REG; /**< HWCE Job_Config0 register, offset: 0x80 */ 1284 __IO uint32_t HWCE_JOB_CONFIG1_REG; /**< HWCE Job_Config1 register, offset: 0x84 */ 1285 } HWCE_Type; 1286 1287 1288 /* ---------------------------------------------------------------------------- 1289 -- HWCE Register Masks 1290 ---------------------------------------------------------------------------- */ 1291 1292 /*! 1293 * @addtogroup HWCE_Register_Masks HWCE Register Masks 1294 * @{ 1295 */ 1296 /*! @name INFO - HWCE information register */ 1297 /* Internal registers */ 1298 #define HWCE_TRIGGER ( 0x00 ) 1299 #define HWCE_ACQUIRE ( 0x04 ) 1300 #define HWCE_FINISHED ( 0x08 ) 1301 #define HWCE_STATUS ( 0x0C ) 1302 #define HWCE_RUNNING_JOB ( 0x10 ) 1303 #define HWCE_SOFT_CLEAR ( 0x14 ) 1304 #define HWCE_GEN_CONFIG0 ( 0x20 ) 1305 #define HWCE_GEN_CONFIG1 ( 0x24 ) 1306 1307 /* Configuration registers */ 1308 #define HWCE_Y_TRANS_SIZE ( 0x40 ) 1309 #define HWCE_Y_LINE_STRIDE_LENGTH ( 0x44 ) 1310 #define HWCE_Y_FEAT_STRIDE_LENGTH ( 0x48 ) 1311 #define HWCE_Y_OUT_3_BASE_ADDR ( 0x4C ) 1312 #define HWCE_Y_OUT_2_BASE_ADDR ( 0x50 ) 1313 #define HWCE_Y_OUT_1_BASE_ADDR ( 0x54 ) 1314 #define HWCE_Y_OUT_0_BASE_ADDR ( 0x58 ) 1315 #define HWCE_Y_IN_3_BASE_ADDR ( 0x5C ) 1316 #define HWCE_Y_IN_2_BASE_ADDR ( 0x60 ) 1317 #define HWCE_Y_IN_1_BASE_ADDR ( 0x64 ) 1318 #define HWCE_Y_IN_0_BASE_ADDR ( 0x68 ) 1319 #define HWCE_X_TRANS_SIZE ( 0x6C ) 1320 #define HWCE_X_LINE_STRIDE_LENGTH ( 0x70 ) 1321 #define HWCE_X_FEAT_STRIDE_LENGTH ( 0x74 ) 1322 #define HWCE_X_IN_BASE_ADDR ( 0x78 ) 1323 #define HWCE_W_BASE_ADDR ( 0x7C ) 1324 #define HWCE_JOB_CONFIG0 ( 0x80 ) 1325 #define HWCE_JOB_CONFIG1 ( 0x84 ) 1326 1327 #define HWCE_NB_IO_REGS ( 18 ) 1328 1329 #define HWCE_ACQUIRE_CONTEXT_COPY ( -3 ) 1330 #define HWCE_ACQUIRE_LOCKED ( -2 ) 1331 #define HWCE_ACQUIRE_QUEUE_FULL ( -1 ) 1332 #define HWCE_ACQUIRE_READY ( 0 ) 1333 1334 #define HWCE_GEN_CONFIG0_WSTRIDE(x) ((x) >> 16) 1335 #define HWCE_GEN_CONFIG0_NCP(x) (((x) >> 13) & 0x1) 1336 #define HWCE_GEN_CONFIG0_CONV(x) (((x) >> 11) & 0x3) 1337 #define HWCE_GEN_CONFIG0_VECT(x) (((x) >> 9) & 0x3) 1338 #define HWCE_GEN_CONFIG0_UNS(x) (((x) >> 8) & 1) 1339 #define HWCE_GEN_CONFIG0_NY(x) (((x) >> 7) & 1) 1340 #define HWCE_GEN_CONFIG0_NF(x) (((x) >> 6) & 1) 1341 #define HWCE_GEN_CONFIG0_QF(x) ((x) & 0x3f) 1342 1343 #define HWCE_GEN_CONFIG0_CONV_5x5 ( 0 ) 1344 #define HWCE_GEN_CONFIG0_CONV_3x3 ( 1 ) 1345 #define HWCE_GEN_CONFIG0_CONV_4x7 ( 2 ) 1346 1347 #define HWCE_GEN_CONFIG0_VECT_1 ( 0 ) 1348 #define HWCE_GEN_CONFIG0_VECT_2 ( 1 ) 1349 #define HWCE_GEN_CONFIG0_VECT_4 ( 2 ) 1350 1351 #define HWCE_GEN_CONFIG1_PIXSHIFTR(x) (((x) >> 16) & 0x1F) 1352 #define HWCE_GEN_CONFIG1_PIXMODE(x) (((x) >> 8) & 0x3) 1353 #define HWCE_GEN_CONFIG1_PIXSHIFTL(x) (((x) >> 0) & 0x1F) 1354 1355 #define HWCE_JOB_CONFIG0_NOYCONST(x) ((x) >> 16) 1356 #define HWCE_JOB_CONFIG0_LBUFLEN(x) ((x) & 0x3ff) 1357 1358 #define HWCE_JOB_CONFIG1_LO(x) (((x) >> 24) & 0x1) 1359 #define HWCE_JOB_CONFIG1_WIF(x) (((x) >> 16) & 0x3F) 1360 #define HWCE_JOB_CONFIG1_WOF(x) (((x) >> 8) & 0x1F) 1361 #define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK(x) (((x) >> 0) & 0xF) 1362 1363 #define HWCE_JOB_STRIDE(x) ((x) >> 16) 1364 #define HWCE_JOB_LENGTH(x) ((x) & 0xffff) 1365 1366 /*! 1367 * @} 1368 */ /* end of group HWCE_Register_Masks */ 1369 1370 1371 /* HWCE - Peripheral instance base addresses */ 1372 /** Peripheral HWCE base address */ 1373 #define HWCE_BASE (CORE_PERI_BASE + 0x00001000) 1374 /** Peripheral HWCE base pointer */ 1375 #define HWCE ((HWCE_Type *) HWCE_BASE) 1376 /** Array initializer of HWCE base addresses */ 1377 #define HWCE_BASE_ADDRS { HWCE_BASE } 1378 /** Array initializer of HWCE base pointers */ 1379 #define HWCE_BASE_PTRS { HWCE } 1380 1381 /*! 1382 * @} 1383 */ /* end of group HWCE_Peripheral_Access_Layer */ 1384 1385 1386 #endif 1387 1388 1389 /* 1390 ** End of section using anonymous unions 1391 */ 1392 1393 /*! 1394 * @} 1395 */ /* end of group Peripheral_access_layer */ 1396 1397 /* ---------------------------------------------------------------------------- 1398 -- SDK Compatibility 1399 ---------------------------------------------------------------------------- */ 1400 1401 /*! 1402 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 1403 * @{ 1404 */ 1405 1406 /*! 1407 * @} 1408 */ /* end of group SDK_Compatibility_Symbols */ 1409 1410 1411 1412 1413 1414 #endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PERIPH_H_ */ 1415