1 /* 2 * This is a generated file 3 * 4 * Copyright 2021 QuickLogic 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 * SPDX-License-Identifier: Apache-2.0 19 */ 20 21 #ifndef __HAL_APB_I2CS_H__ 22 #define __HAL_APB_I2CS_H__ 23 24 #include "stdint.h" 25 26 #define MY_I2C_SLAVE_ADDRESS 0x62 27 #define MY_I2C_SLAVE_ADDRESS_7BIT (0x62 << 1) 28 29 #define I2C_MASTER_REG_DEV_ADDRESS 0x00 30 #define I2C_MASTER_REG_ENABLE 0x01 31 #define I2C_MASTER_REG_DEBOUNCE_LENGTH 0x02 32 #define I2C_MASTER_REG_SCL_DELAY_LENGTH 0x03 33 #define I2C_MASTER_REG_SDA_DELAY_LENGTH 0x04 34 #define I2C_MASTER_REG_MSG_I2C_APB 0x10 35 #define I2C_MASTER_REG_MSG_I2C_APB_STATUS 0x11 36 #define I2C_MASTER_REG_MSG_APB_I2C 0x12 37 #define I2C_MASTER_REG_MSG_APB_I2C_STATUS 0x13 38 #define I2C_MASTER_REG_FIFO_I2C_APB_WRITE_DATA_PORT 0x20 39 #define I2C_MASTER_REG_FIFO_I2C_APB_READ_DATA_PORT 0x21 40 #define I2C_MASTER_REG_FIFO_I2C_APB_FLUSH 0x22 41 #define I2C_MASTER_REG_FIFO_I2C_APB_WRITE_FLAGS 0x23 42 #define I2C_MASTER_REG_FIFO_I2C_APB_READ_FLAGS 0x24 43 #define I2C_MASTER_REG_FIFO_APB_I2C_WRITE_DATA_PORT 0x30 44 #define I2C_MASTER_REG_FIFO_APB_I2C_READ_DATA_PORT 0x31 45 #define I2C_MASTER_REG_FIFO_APB_I2C_FLUSH 0x32 46 #define I2C_MASTER_REG_FIFO_APB_I2C_WRITE_FLAGS 0x33 47 #define I2C_MASTER_REG_FIFO_APB_I2C_READ_FLAGS 0x34 48 #define I2C_MASTER_REG_INTERRUPT_STATUS 0x40 49 #define I2C_MASTER_REG_INTERRUPT_ENABLE 0x41 50 #define I2C_MASTER_REG_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT 0x42 51 #define I2C_MASTER_REG_INTERRUPT_APB_I2C_READ_FLAGS_SELECT 0x43 52 #define I2C_MASTER_REG_INTERRUPT_TO_APB_STATUS 0x50 53 #define I2C_MASTER_REG_INTERRUPT_TO_APB_ENABLE 0x51 54 #define I2C_MASTER_REG_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT 0x52 55 #define I2C_MASTER_REG_INTERRUPT_I2C_APB_READ_FLAGS_SELECT 0x53 56 57 uint8_t hal_get_apb_i2cs_slave_address(void); 58 void hal_set_apb_i2cs_slave_address(uint8_t aSlaveAddress); 59 uint8_t hal_set_apb_i2cs_slave_on_off(uint8_t aStatus); 60 uint8_t hal_get_i2cs_fifo_i2c_apb_read_data_port(void); 61 void hal_set_i2cs_fifo_apb_i2c_write_data_port(uint8_t aData); 62 uint8_t hal_get_i2cs_fifo_i2c_apb_write_flags(void); 63 uint8_t hal_get_i2cs_fifo_i2c_apb_read_flags(void); 64 uint8_t hal_get_i2cs_fifo_apb_i2c_read_flags(void); 65 uint8_t hal_get_i2cs_fifo_apb_i2c_write_flags(void); 66 uint8_t hal_get_i2cs_msg_i2c_apb(void); 67 uint8_t hal_get_i2cs_msg_i2c_apb_status(void); 68 void hal_set_i2cs_msg_apb_i2c(uint8_t aData); 69 uint8_t hal_get_i2cs_msg_apb_i2c_status(void); 70 void hal_i2cs_fifo_i2c_apb_FIFO_flush(void); 71 void hal_i2cs_fifo_apb_i2c_FIFO_flush(void); 72 73 74 #endif // __HAL_APB_I2CS_H__ 75