| /bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/ |
| A D | system_interrupt.c | 69 result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0); in system_interrupt_is_pending()
104 SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk; in system_interrupt_set_pending()
106 SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; in system_interrupt_set_pending()
142 SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; in system_interrupt_clear_pending()
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| /bsp/rockchip/common/rk_hal/lib/hal/src/pm/ |
| A D | hal_pm_cpu.c | 225 scbSave.ICSR = SCB->ICSR; in HAL_SCB_SuspendSave()
247 SCB->ICSR = scbSave.ICSR; in HAL_SCB_ResumeRestore()
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| /bsp/microchip/samc21/bsp/hri/ |
| A D | hri_systemcontrol_c21.h | 160 ((Systemcontrol *)hw)->ICSR.reg |= mask; in hri_systemcontrol_set_ICSR_reg()
168 tmp = ((Systemcontrol *)hw)->ICSR.reg; in hri_systemcontrol_get_ICSR_reg()
176 ((Systemcontrol *)hw)->ICSR.reg = data; in hri_systemcontrol_write_ICSR_reg()
183 ((Systemcontrol *)hw)->ICSR.reg &= ~mask; in hri_systemcontrol_clear_ICSR_reg()
190 ((Systemcontrol *)hw)->ICSR.reg ^= mask; in hri_systemcontrol_toggle_ICSR_reg()
196 return ((Systemcontrol *)hw)->ICSR.reg; in hri_systemcontrol_read_ICSR_reg()
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| /bsp/yichip/yc3121-pos/Libraries/core/ |
| A D | misc.c | 24 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ member
84 SCB->ICSR |= (1 << SBC_ICSR_PENDSV_IRQ); in trigger_PendSV()
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| /bsp/microchip/samd51-adafruit-metro-m4/bsp/hpl/core/ |
| A D | hpl_core_port.h | 56 return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); in _is_in_isr()
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| /bsp/microchip/samc21/bsp/hpl/core/ |
| A D | hpl_core_port.h | 56 return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); in _is_in_isr()
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| /bsp/microchip/samd51-seeed-wio-terminal/bsp/hpl/core/ |
| A D | hpl_core_port.h | 56 return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); in _is_in_isr()
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| /bsp/microchip/saml10/bsp/hpl/core/ |
| A D | hpl_core_port.h | 56 return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); in _is_in_isr()
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| /bsp/microchip/same54/bsp/hpl/core/ |
| A D | hpl_core_port.h | 56 return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); in _is_in_isr()
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| /bsp/microchip/same70/bsp/hpl/core/ |
| A D | hpl_core_port.h | 82 return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); in _is_in_isr()
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| /bsp/airm2m/air105/libraries/HAL_Driver/Src/ |
| A D | core_irq.c | 42 …int IrqLine = ((SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos) - IRQ_LINE_OFFSET; in ISR_GlobalHandler()
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| /bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/ |
| A D | ht32_cm3_misc.c | 130 SCB->ICSR |= SystemHandler; in NVIC_SetPendingSystemHandler()
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| /bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/ |
| A D | ht32_cm0plus_misc.c | 122 SCB->ICSR |= SystemHandler; in NVIC_SetPendingSystemHandler()
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| /bsp/fujitsu/mb9x/mb9bf568r/CMSIS/Include/ |
| A D | core_cm0.h | 295 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/efm32/Libraries/CMSIS/Include/ |
| A D | core_cm0.h | 293 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/CME_M7/CMSIS/CMSIS/Include/ |
| A D | core_cm0.h | 308 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/ |
| A D | core_cm0.h | 308 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/mm32l07x/Libraries/CMSIS/CORE/ |
| A D | core_cm0.h | 293 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/mm32l3xx/Libraries/CMSIS/KEIL_CORE/ |
| A D | core_cm0.h | 293 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/Core/ |
| A D | core_cm0.h | 308 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/nxp/lpc/lpc43xx/Libraries/CMSIS/Include/ |
| A D | core_cm0.h | 308 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/ |
| A D | core_cm0.h | 283 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/xplorer4330/Libraries/CMSIS/Include/ |
| A D | core_cm0.h | 308 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/essemi/es32f0654/libraries/CMSIS/Include/ |
| A D | core_cm0.h | 294 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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| /bsp/synwit/libraries/SWM320_CSL/CMSIS/CoreSupport/ |
| A D | core_cm0.h | 337 …__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis… member
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