Searched refs:IC_INTR_MASK (Results 1 – 16 of 16) sorted by relevance
130 I2C->IC_INTR_MASK = I2C_IC_INTR_MASK_M_RX_FULL|I2C_IC_INTR_MASK_M_STOP_DET; in I2C_IrqHandle()159 I2C->IC_INTR_MASK = 0; in I2C_IrqHandle()208 I2C->IC_INTR_MASK = 0; in I2C_IrqHandleRegQueue()248 I2C->IC_INTR_MASK = 0; in I2C_MasterSetup()285 I2C->IC_INTR_MASK = 0; in I2C_MasterXfer()314 I2C->IC_INTR_MASK = I2C_IC_INTR_MASK_M_TX_EMPTY|I2C_IC_INTR_MASK_M_STOP_DET; in I2C_MasterXfer()326 I2C->IC_INTR_MASK = I2C_IC_INTR_MASK_M_RX_FULL|I2C_IC_INTR_MASK_M_STOP_DET; in I2C_MasterXfer()339 I2C->IC_INTR_MASK = I2C_IC_INTR_MASK_M_TX_EMPTY|I2C_IC_INTR_MASK_M_STOP_DET; in I2C_MasterXfer()356 I2C->IC_INTR_MASK = 0; in I2C_MasterWriteRegQueue()383 I2C->IC_INTR_MASK = I2C_IC_INTR_MASK_M_TX_EMPTY|I2C_IC_INTR_MASK_M_STOP_DET; in I2C_MasterWriteRegQueue()[all …]
166 addr->IC_INTR_MASK &= ~(1 << DW_IIC_TX_EMPTY); in dw_iic_intr_tx_empty()346 addr->IC_INTR_MASK = 0x00; in csi_iic_initialize()348 addr->IC_INTR_MASK |= 1 << DW_IIC_TX_ABRT; in csi_iic_initialize()349 addr->IC_INTR_MASK |= 1 << DW_IIC_TX_OVER; in csi_iic_initialize()350 addr->IC_INTR_MASK |= 1 << DW_IIC_RX_OVER; in csi_iic_initialize()351 addr->IC_INTR_MASK |= 1 << DW_IIC_RX_FULL; in csi_iic_initialize()352 addr->IC_INTR_MASK |= 1 << DW_IIC_STOP_DET; in csi_iic_initialize()373 addr->IC_INTR_MASK = 0x00; in csi_iic_uninitialize()513 addr->IC_INTR_MASK |= 1 << DW_IIC_TX_EMPTY; in csi_iic_master_send()
92 __IOM uint32_t IC_INTR_MASK; /* Offset: 0x030 (R/W) Transmission state register */ member
205 tmpreg = I2Cx->IC_INTR_MASK; in I2C_Init()209 I2Cx->IC_INTR_MASK = tmpreg; in I2C_Init()454 I2Cx->IC_INTR_MASK |= I2C_IT; in I2C_ITConfig()459 I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_IT; in I2C_ITConfig()834 I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_IT; in I2C_ClearITPendingBit()
396 volatile uint32_t IC_INTR_MASK; /* Offset: 0x030 (R/W) I2C Interrupt Mask */ member452 iic_base->IC_INTR_MASK = DW_IIC_INTR_TX_EMPTY | DW_IIC_INTR_TX_OVER | DW_IIC_INTR_STOP_DET; in dw_iic_master_enable_transmit_irq()458 iic_base->IC_INTR_MASK = DW_IIC_INTR_RD_REQ | DW_IIC_INTR_STOP_DET; in dw_iic_slave_enable_transmit_irq()464 iic_base->IC_INTR_MASK = DW_IIC_INTR_STOP_DET | DW_IIC_INTR_RX_FULL | DW_IIC_INTR_RX_OVER; in dw_iic_master_enable_receive_irq()470 iic_base->IC_INTR_MASK = DW_IIC_INTR_STOP_DET | DW_IIC_INTR_RX_FULL; in dw_iic_slave_enable_receive_irq()639 iic_base->IC_INTR_MASK = 0U; in dw_iic_disable_all_irq()
217 tmpreg = I2Cx->IC_INTR_MASK; in I2C_Init()221 I2Cx->IC_INTR_MASK = tmpreg; in I2C_Init()463 I2Cx->IC_INTR_MASK |= I2C_IT; in I2C_ITConfig()468 I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_IT; in I2C_ITConfig()
205 tmpreg = I2Cx->IC_INTR_MASK; in I2C_Init()209 I2Cx->IC_INTR_MASK = tmpreg; in I2C_Init()446 I2Cx->IC_INTR_MASK |= I2C_IT; in I2C_ITConfig()451 I2Cx->IC_INTR_MASK &= (uint16_t)~I2C_IT; in I2C_ITConfig()
105 i2c->IC_INTR_MASK &= INTR_MASK; in I2C_Init()248 (state) ? SET_BIT(i2c->IC_INTR_MASK, it) : CLEAR_BIT(i2c->IC_INTR_MASK, (u16)it); in I2C_ITConfig()
102 __IO u32 IC_INTR_MASK; member263 __IO u32 IC_INTR_MASK; member
148 __IOM uint32_t IC_INTR_MASK; /* Offset: 0x030 (R/W) Transmission state register */
679 __IO uint32_t IC_INTR_MASK; member
528 __IO uint16_t IC_INTR_MASK; member
537 __IO uint16_t IC_INTR_MASK; member
595 __IO uint16_t IC_INTR_MASK; member
512 __IO uint16_t IC_INTR_MASK; member
Completed in 127 milliseconds