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Searched refs:IER (Results 1 – 25 of 226) sorted by relevance

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/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/
A Dfm33lc0xx_fl_rtc.h265 SET_BIT(RTCx->IER, RTC_IER_ADJ_IE_Msk); in FL_RTC_EnableIT_Adjust()
331 SET_BIT(RTCx->IER, RTC_IER_1KHZ_IE_Msk); in FL_RTC_EnableIT_1KHz()
397 SET_BIT(RTCx->IER, RTC_IER_64HZ_IE_Msk); in FL_RTC_EnableIT_64Hz()
430 SET_BIT(RTCx->IER, RTC_IER_16HZ_IE_Msk); in FL_RTC_EnableIT_16Hz()
463 SET_BIT(RTCx->IER, RTC_IER_8HZ_IE_Msk); in FL_RTC_EnableIT_8Hz()
496 SET_BIT(RTCx->IER, RTC_IER_4HZ_IE_Msk); in FL_RTC_EnableIT_4Hz()
529 SET_BIT(RTCx->IER, RTC_IER_2HZ_IE_Msk); in FL_RTC_EnableIT_2Hz()
562 SET_BIT(RTCx->IER, RTC_IER_SEC_IE_Msk); in FL_RTC_EnableIT_Second()
595 SET_BIT(RTCx->IER, RTC_IER_MIN_IE_Msk); in FL_RTC_EnableIT_Minute()
628 SET_BIT(RTCx->IER, RTC_IER_HOUR_IE_Msk); in FL_RTC_EnableIT_Hour()
[all …]
A Dfm33lc0xx_fl_flash.h587 SET_BIT(FLASHx->IER, FLASH_IER_OPTIE_Msk); in FL_FLASH_EnableIT_OTPProgramError()
598 CLEAR_BIT(FLASHx->IER, FLASH_IER_OPTIE_Msk); in FL_FLASH_DisableIT_OTPProgramError()
620 SET_BIT(FLASHx->IER, FLASH_IER_AUTHIE_Msk); in FL_FLASH_EnableIT_AuthenticationError()
653 SET_BIT(FLASHx->IER, FLASH_IER_KEYIE_Msk); in FL_FLASH_EnableIT_KeyError()
664 CLEAR_BIT(FLASHx->IER, FLASH_IER_KEYIE_Msk); in FL_FLASH_DisableIT_KeyError()
686 SET_BIT(FLASHx->IER, FLASH_IER_CKIE_Msk); in FL_FLASH_EnableIT_ClockError()
697 CLEAR_BIT(FLASHx->IER, FLASH_IER_CKIE_Msk); in FL_FLASH_DisableIT_ClockError()
719 SET_BIT(FLASHx->IER, FLASH_IER_PRDIE_Msk); in FL_FLASH_EnableIT_ProgramComplete()
730 CLEAR_BIT(FLASHx->IER, FLASH_IER_PRDIE_Msk); in FL_FLASH_DisableIT_ProgramComplete()
752 SET_BIT(FLASHx->IER, FLASH_IER_ERDIE_Msk); in FL_FLASH_EnableIT_EraseComplete()
[all …]
A Dfm33lc0xx_fl_uart.h762 SET_BIT(UARTx->IER, UART_IER_RXTOIE_Msk); in FL_UART_EnableIT_RXTimeout()
773 CLEAR_BIT(UARTx->IER, UART_IER_RXTOIE_Msk); in FL_UART_DisableIT_RXTimeout()
795 SET_BIT(UARTx->IER, UART_IER_RXERRIE_Msk); in FL_UART_EnableIT_RXError()
806 CLEAR_BIT(UARTx->IER, UART_IER_RXERRIE_Msk); in FL_UART_DisableIT_RXError()
828 SET_BIT(UARTx->IER, UART_IER_RXBFIE_Msk); in FL_UART_EnableIT_RXBuffFull()
839 CLEAR_BIT(UARTx->IER, UART_IER_RXBFIE_Msk); in FL_UART_DisableIT_RXBuffFull()
861 SET_BIT(UARTx->IER, UART_IER_NEWUPIE_Msk); in FL_UART_EnableIT_FallingEdgeWakeup()
894 SET_BIT(UARTx->IER, UART_IER_TXBEIE_Msk); in FL_UART_EnableIT_TXBuffEmpty()
905 CLEAR_BIT(UARTx->IER, UART_IER_TXBEIE_Msk); in FL_UART_DisableIT_TXBuffEmpty()
927 SET_BIT(UARTx->IER, UART_IER_TXSEIE_Msk); in FL_UART_EnableIT_TXShiftBuffEmpty()
[all …]
A Dfm33lc0xx_fl_lpuart.h625 SET_BIT(LPUARTx->IER, LPUART_IER_RXEV_IE_Msk); in FL_LPUART_EnableIT_RXWakeup()
636 return (uint32_t)(READ_BIT(LPUARTx->IER, LPUART_IER_RXEV_IE_Msk) == LPUART_IER_RXEV_IE_Msk); in FL_LPUART_IsEnabledIT_RXWakeup()
647 CLEAR_BIT(LPUARTx->IER, LPUART_IER_RXEV_IE_Msk); in FL_LPUART_DisableIT_RXWakeup()
658 SET_BIT(LPUARTx->IER, LPUART_IER_RXERR_IE_Msk); in FL_LPUART_EnableIT_RXError()
680 CLEAR_BIT(LPUARTx->IER, LPUART_IER_RXERR_IE_Msk); in FL_LPUART_DisableIT_RXError()
691 SET_BIT(LPUARTx->IER, LPUART_IER_RXBF_IE_Msk); in FL_LPUART_EnableIT_RXBuffFull()
713 CLEAR_BIT(LPUARTx->IER, LPUART_IER_RXBF_IE_Msk); in FL_LPUART_DisableIT_RXBufFull()
724 SET_BIT(LPUARTx->IER, LPUART_IER_TXBE_IE_Msk); in FL_LPUART_EnableIT_TXBuffEmpty()
746 CLEAR_BIT(LPUARTx->IER, LPUART_IER_TXBE_IE_Msk); in FL_LPUART_DisableIT_TXBuffEmpty()
757 SET_BIT(LPUARTx->IER, LPUART_IER_TXSE_IE_Msk); in FL_LPUART_EnableIT_TXShiftBuffEmpty()
[all …]
A Dfm33lc0xx_fl_aes.h384 SET_BIT(AESx->IER, AES_IER_WRERR_IE_Msk); in FL_AES_EnableIT_WriteError()
395 return (uint32_t)(READ_BIT(AESx->IER, AES_IER_WRERR_IE_Msk) == AES_IER_WRERR_IE_Msk); in FL_AES_IsEnabledIT_WriteError()
406 CLEAR_BIT(AESx->IER, AES_IER_WRERR_IE_Msk); in FL_AES_DisableIT_WriteError()
417 SET_BIT(AESx->IER, AES_IER_RDERR_IE_Msk); in FL_AES_EnableIT_ReadError()
428 return (uint32_t)(READ_BIT(AESx->IER, AES_IER_RDERR_IE_Msk) == AES_IER_RDERR_IE_Msk); in FL_AES_IsEnabledIT_ReadError()
439 CLEAR_BIT(AESx->IER, AES_IER_RDERR_IE_Msk); in FL_AES_DisableIT_ReadError()
450 SET_BIT(AESx->IER, AES_IER_CCF_IE_Msk); in FL_AES_EnableIT_Complete()
461 return (uint32_t)(READ_BIT(AESx->IER, AES_IER_CCF_IE_Msk) == AES_IER_CCF_IE_Msk); in FL_AES_IsEnabledIT_Complete()
472 CLEAR_BIT(AESx->IER, AES_IER_CCF_IE_Msk); in FL_AES_DisableIT_Complete()
A Dfm33lc0xx_fl_pmu.h713 SET_BIT(PMUx->IER, PMU_IER_LPRUNEIE_Msk); in FL_PMU_EnableIT_LPRunError()
724 return (uint32_t)(READ_BIT(PMUx->IER, PMU_IER_LPRUNEIE_Msk) == PMU_IER_LPRUNEIE_Msk); in FL_PMU_IsEnabledIT_LPRunError()
735 CLEAR_BIT(PMUx->IER, PMU_IER_LPRUNEIE_Msk); in FL_PMU_DisableIT_LPRunError()
746 SET_BIT(PMUx->IER, PMU_IER_LPACTEIE_Msk); in FL_PMU_EnableIT_LPActiveError()
768 CLEAR_BIT(PMUx->IER, PMU_IER_LPACTEIE_Msk); in FL_PMU_DisableIT_LPActiveError()
779 SET_BIT(PMUx->IER, PMU_IER_SLPEIE_Msk); in FL_PMU_EnableIT_SleepError()
790 return (uint32_t)(READ_BIT(PMUx->IER, PMU_IER_SLPEIE_Msk) == PMU_IER_SLPEIE_Msk); in FL_PMU_IsEnabledIT_SleepError()
801 CLEAR_BIT(PMUx->IER, PMU_IER_SLPEIE_Msk); in FL_PMU_DisableIT_SleepError()
812 SET_BIT(PMUx->IER, PMU_IER_RTCEIE_Msk); in FL_PMU_EnableIT_RTCBKPError()
823 return (uint32_t)(READ_BIT(PMUx->IER, PMU_IER_RTCEIE_Msk) == PMU_IER_RTCEIE_Msk); in FL_PMU_IsEnabledIT_RTCBKPError()
[all …]
A Dfm33lc0xx_fl_adc.h539 SET_BIT(ADCx->IER, ADC_IER_EOCIE_Msk); in FL_ADC_EnableIT_EndOfConversion()
550 CLEAR_BIT(ADCx->IER, ADC_IER_EOCIE_Msk); in FL_ADC_DisableIT_EndOfConversion()
561 return (uint32_t)(READ_BIT(ADCx->IER, ADC_IER_EOCIE_Msk) == ADC_IER_EOCIE_Msk); in FL_ADC_IsEnabledIT_EndOfConversion()
572 SET_BIT(ADCx->IER, ADC_IER_EOSIE_Msk); in FL_ADC_EnableIT_EndOfSequence()
583 CLEAR_BIT(ADCx->IER, ADC_IER_EOSIE_Msk); in FL_ADC_DisableIT_EndOfSequence()
605 SET_BIT(ADCx->IER, ADC_IER_OVRIE_Msk); in FL_ADC_EnableIT_Overrun()
616 CLEAR_BIT(ADCx->IER, ADC_IER_OVRIE_Msk); in FL_ADC_DisableIT_Overrun()
638 SET_BIT(ADCx->IER, ADC_IER_AWD_ULIE_Msk); in FL_ADC_EnableIT_AnalogWDGUnderLow()
649 CLEAR_BIT(ADCx->IER, ADC_IER_AWD_ULIE_Msk); in FL_ADC_DisableIT_AnalogWDGUnderLow()
671 SET_BIT(ADCx->IER, ADC_IER_AWD_AHIE_Msk); in FL_ADC_EnableIT_AnalogWDGAboveHigh()
[all …]
A Dfm33lc0xx_fl_lptim32.h626 SET_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x0U)); in FL_LPTIM32_EnableIT_CC()
637 SET_BIT(LPTIM32x->IER, LPTIM32_IER_OVIE_Msk); in FL_LPTIM32_EnableIT_Update()
648 SET_BIT(LPTIM32x->IER, LPTIM32_IER_TRIGIE_Msk); in FL_LPTIM32_EnableIT_Trigger()
662 SET_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x8U)); in FL_LPTIM32_EnableIT_CCOverflow()
676 CLEAR_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x0U)); in FL_LPTIM32_DisableIT_CC()
687 CLEAR_BIT(LPTIM32x->IER, LPTIM32_IER_OVIE_Msk); in FL_LPTIM32_DisableIT_Update()
698 CLEAR_BIT(LPTIM32x->IER, LPTIM32_IER_TRIGIE_Msk); in FL_LPTIM32_DisableIT_Trigger()
712 CLEAR_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x8U)); in FL_LPTIM32_DisableIT_CCOverflow()
726 …return (uint32_t)(READ_BIT(LPTIM32x->IER, ((channel & 0x3) << 0x0U)) == ((channel & 0x3) << 0x0U)); in FL_LPTIM32_IsEnabledIT_CC()
737 return (uint32_t)(READ_BIT(LPTIM32x->IER, LPTIM32_IER_OVIE_Msk) == LPTIM32_IER_OVIE_Msk); in FL_LPTIM32_IsEnabledIT_Update()
[all …]
/bsp/rx/drivers/
A Duart.c388 ICU.IER[IER_SCI0_ERI0].BIT.IEN_SCI0_ERI0 = 1; in rx_configure()
389 ICU.IER[IER_SCI0_RXI0].BIT.IEN_SCI0_RXI0 = 1; in rx_configure()
390 ICU.IER[IER_SCI0_TEI0].BIT.IEN_SCI0_TEI0 = 1; in rx_configure()
391 ICU.IER[IER_SCI0_TXI0].BIT.IEN_SCI0_TXI0 = 1; in rx_configure()
396 ICU.IER[IER_SCI1_ERI1].BIT.IEN_SCI1_ERI1 = 1; in rx_configure()
397 ICU.IER[IER_SCI1_RXI1].BIT.IEN_SCI1_RXI1 = 1; in rx_configure()
404 ICU.IER[IER_SCI2_ERI2].BIT.IEN_SCI2_ERI2 = 1; in rx_configure()
405 ICU.IER[IER_SCI2_RXI2].BIT.IEN_SCI2_RXI2 = 1; in rx_configure()
406 ICU.IER[IER_SCI2_RXI2].BIT.IEN_SCI2_TEI2 = 0; in rx_configure()
407 ICU.IER[IER_SCI2_TXI2].BIT.IEN_SCI2_TXI2 = 0; in rx_configure()
[all …]
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/src/
A Dht32f5xxxx_usbd.c110 pDriver->ept[USBD_EPT0].IER = _EP0_IER; in USBD_PreInit()
114 pDriver->ept[USBD_EPT1].IER = _EP1_IER; in USBD_PreInit()
119 pDriver->ept[USBD_EPT2].IER = _EP2_IER; in USBD_PreInit()
124 pDriver->ept[USBD_EPT3].IER = _EP3_IER; in USBD_PreInit()
338 HT_USB->IER |= INTFlag; in USBD_EnableINT()
351 HT_USB->IER &= (~INTFlag); in USBD_DisableINT()
361 u32 IER = HT_USB->IER | FRESIE; in USBD_GetINT() local
362 return (HT_USB->ISR & IER); in USBD_GetINT()
412 USBEPn->IER = pDrv->ept[USBD_EPTn].IER; in USBD_EPTInit()
458 u32 IER = USBEPn->IER; in USBD_EPTGetINT() local
[all …]
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/src/
A Dht32f1xxxx_usbd.c110 pDriver->ept[USBD_EPT0].IER = _EP0_IER; in USBD_PreInit()
114 pDriver->ept[USBD_EPT1].IER = _EP1_IER; in USBD_PreInit()
119 pDriver->ept[USBD_EPT2].IER = _EP2_IER; in USBD_PreInit()
124 pDriver->ept[USBD_EPT3].IER = _EP3_IER; in USBD_PreInit()
327 HT_USB->IER |= INTFlag; in USBD_EnableINT()
340 HT_USB->IER &= (~INTFlag); in USBD_DisableINT()
350 u32 IER = HT_USB->IER | FRESIE; in USBD_GetINT() local
351 return (HT_USB->ISR & IER); in USBD_GetINT()
401 USBEPn->IER = pDrv->ept[USBD_EPTn].IER; in USBD_EPTInit()
447 u32 IER = USBEPn->IER; in USBD_EPTGetINT() local
[all …]
/bsp/airm2m/air105/libraries/HAL_Driver/Src/
A Dcore_uart.c84 UARTx->OFFSET_4.IER |= UART_IER_PTIME; in prvUart_FIFOInit()
88 UARTx->OFFSET_4.IER &= ~UART_IER_PTIME; in prvUart_FIFOInit()
198 Uart->OFFSET_4.IER = UART_IER_ELSI; in Uart_BaseInit()
218 Uart->OFFSET_4.IER = 0; in Uart_DeInit()
263 Uart->OFFSET_4.IER &= ~(UART_IER_PTIME|UART_IER_ETBEI); in Uart_BlockTx()
289 Uart->OFFSET_4.IER |= UART_IT_RX_RECVD|UART_IER_ELSI; in Uart_EnableRxIrq()
305 Uart->OFFSET_4.IER |= UART_IER_PTIME|UART_IER_ETBEI; in Uart_DMATx()
312 Uart->OFFSET_4.IER |= UART_IT_RX_RECVD; in Uart_DMARx()
516 if (Uart->OFFSET_4.IER & UART_IER_PTIME) in prvUart_Tx()
518 Uart->OFFSET_4.IER &= ~UART_IER_PTIME; in prvUart_Tx()
[all …]
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/CMSIS/Include/
A Dfm33lg0xx.h157 …__IO uint32_t IER; /*!< Flash Interrupt Enable Register, … member
171 …__IO uint32_t IER; /*!< PMU Interrupt Enable Register, … member
202 …__IO uint32_t IER; /*!< VREF Interrupt Enable Register, … member
269 …__IO uint32_t IER; /*!< IWDT Interrupt Enable Register, … member
283 …__IO uint32_t IER; /*!< WWDT Interrupt Enable Register, … member
306 …__IO uint32_t IER; /*!< Interrupt Enable Register, … member
331 …__IO uint32_t IER; /*!< SVD Interrupt Enable Register, … member
344 …__IO uint32_t IER; /*!< AES Interrupt Enable Register, … member
469 …__IO uint32_t IER; /*!< UARTx Interrupt Enable Register, … member
683 …__IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, A… member
[all …]
A Dfm33lc0xx.h125 …__IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address … member
138 …__IO uint32_t IER; /*!< AES Interrupt Enable Register, Address … member
190 …__IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, Address … member
272 …__IO uint32_t IER; /*!< Flash Interrupt Enable Register, Address … member
368 …__IO uint32_t IER; /*!< IWDT Status Register, Address … member
379 …__IO uint32_t IER; /*!< LCD Interrupt Enable Register, Address … member
428 __IO uint32_t IER; /*!< OPA Interrupt Enable Register */ member
437 __IO uint32_t IER; /*!< PMU Interrupt Enable Register */ member
534 __IO uint32_t IER; /*!< SPI1 Interrupt Enable Register */ member
647 __IO uint32_t IER; /*!< UART Interrupt Enable Register */ member
[all …]
/bsp/fm33lc026/libraries/FM/FM33xx/Include/
A Dfm33lg0xx.h157 …__IO uint32_t IER; /*!< Flash Interrupt Enable Register, … member
171 …__IO uint32_t IER; /*!< PMU Interrupt Enable Register, … member
202 …__IO uint32_t IER; /*!< VREF Interrupt Enable Register, … member
269 …__IO uint32_t IER; /*!< IWDT Interrupt Enable Register, … member
283 …__IO uint32_t IER; /*!< WWDT Interrupt Enable Register, … member
306 …__IO uint32_t IER; /*!< Interrupt Enable Register, … member
331 …__IO uint32_t IER; /*!< SVD Interrupt Enable Register, … member
344 …__IO uint32_t IER; /*!< AES Interrupt Enable Register, … member
469 …__IO uint32_t IER; /*!< UARTx Interrupt Enable Register, … member
683 …__IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, A… member
[all …]
A Dfm33lc0xx.h125 …__IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address … member
138 …__IO uint32_t IER; /*!< AES Interrupt Enable Register, Address … member
190 …__IO uint32_t IER; /*!< BSTIM Interrupt Enable Register, Address … member
272 …__IO uint32_t IER; /*!< Flash Interrupt Enable Register, Address … member
368 …__IO uint32_t IER; /*!< IWDT Status Register, Address … member
379 …__IO uint32_t IER; /*!< LCD Interrupt Enable Register, Address … member
428 __IO uint32_t IER; /*!< OPA Interrupt Enable Register */ member
437 __IO uint32_t IER; /*!< PMU Interrupt Enable Register */ member
534 __IO uint32_t IER; /*!< SPI1 Interrupt Enable Register */ member
646 __IO uint32_t IER; /*!< UART Interrupt Enable Register */ member
[all …]
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_icm_d51.h237 ((Icm *)hw)->IER.reg = ICM_IMR_URAD; in hri_icm_set_IMR_URAD_bit()
250 ((Icm *)hw)->IER.reg = ICM_IMR_URAD; in hri_icm_write_IMR_URAD_bit()
261 ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); in hri_icm_set_IMR_RHC_bf()
282 ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); in hri_icm_write_IMR_RHC_bf()
293 ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); in hri_icm_set_IMR_RDM_bf()
314 ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); in hri_icm_write_IMR_RDM_bf()
325 ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); in hri_icm_set_IMR_RBE_bf()
346 ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); in hri_icm_write_IMR_RBE_bf()
357 ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); in hri_icm_set_IMR_RWC_bf()
453 ((Icm *)hw)->IER.reg = mask; in hri_icm_set_IMR_reg()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_icm_d51.h237 ((Icm *)hw)->IER.reg = ICM_IMR_URAD; in hri_icm_set_IMR_URAD_bit()
250 ((Icm *)hw)->IER.reg = ICM_IMR_URAD; in hri_icm_write_IMR_URAD_bit()
261 ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); in hri_icm_set_IMR_RHC_bf()
282 ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); in hri_icm_write_IMR_RHC_bf()
293 ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); in hri_icm_set_IMR_RDM_bf()
314 ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); in hri_icm_write_IMR_RDM_bf()
325 ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); in hri_icm_set_IMR_RBE_bf()
346 ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); in hri_icm_write_IMR_RBE_bf()
357 ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); in hri_icm_set_IMR_RWC_bf()
453 ((Icm *)hw)->IER.reg = mask; in hri_icm_set_IMR_reg()
[all …]
/bsp/microchip/same54/bsp/hri/
A Dhri_icm_e54.h237 ((Icm *)hw)->IER.reg = ICM_IMR_URAD; in hri_icm_set_IMR_URAD_bit()
250 ((Icm *)hw)->IER.reg = ICM_IMR_URAD; in hri_icm_write_IMR_URAD_bit()
261 ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); in hri_icm_set_IMR_RHC_bf()
282 ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); in hri_icm_write_IMR_RHC_bf()
293 ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); in hri_icm_set_IMR_RDM_bf()
314 ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); in hri_icm_write_IMR_RDM_bf()
325 ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); in hri_icm_set_IMR_RBE_bf()
346 ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); in hri_icm_write_IMR_RBE_bf()
357 ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); in hri_icm_set_IMR_RWC_bf()
453 ((Icm *)hw)->IER.reg = mask; in hri_icm_set_IMR_reg()
[all …]
A Dhri_pcc_e54.h62 ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; in hri_pcc_set_IMR_DRDY_bit()
75 ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; in hri_pcc_write_IMR_DRDY_bit()
86 ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; in hri_pcc_set_IMR_OVRE_bit()
99 ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; in hri_pcc_write_IMR_OVRE_bit()
110 ((Pcc *)hw)->IER.reg = mask; in hri_pcc_set_IMR_reg()
128 ((Pcc *)hw)->IER.reg = data; in hri_pcc_write_IMR_reg()
/bsp/wch/risc-v/Libraries/ch56x_drivers/
A Dch56x_uart.c156 uxreg->IER.txd_en = 1; in uart_configure()
169 uxreg->IER.recv_rdy = 0; in uart_control()
170 uxreg->IER.line_stat = 0; in uart_control()
171 uxreg->IER.thr_empty = 0; in uart_control()
177 uxreg->IER.recv_rdy = 1; in uart_control()
178 uxreg->IER.line_stat = 1; in uart_control()
181 uxreg->IER.thr_empty = 1; in uart_control()
/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_uart.c132 pUartSave->IER = pReg->IER; in HAL_UART_Suspend()
167 pReg->IER = pUartSave->IER; in HAL_UART_Resume()
322 pReg->IER = 0; in HAL_UART_Reset()
402 pReg->IER |= uartIntNumb; in HAL_UART_EnableIrq()
413 pReg->IER &= ~uartIntNumb; in HAL_UART_DisableIrq()
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/
A Dtae32f53xx_ll_uart.h237 #define __LL_UART_THRE_INT_En(__UART__) SET_BIT((__UART__)->IER, UART_IER_PTIME_Msk)
244 #define __LL_UART_THRE_INT_Dis(__UART__) CLEAR_BIT((__UART__)->IER, UART_IER_PTIME_Msk)
251 #define __LL_UART_ModemSta_INT_En(__UART__) SET_BIT((__UART__)->IER, UART_IER_EDSSI_Msk)
258 #define __LL_UART_ModemSta_INT_Dis(__UART__) CLEAR_BIT((__UART__)->IER, UART_IER_EDSSI_Msk)
265 #define __LL_UART_RxLineSta_INT_En(__UART__) SET_BIT((__UART__)->IER, UART_IER_ELSI_Msk)
272 #define __LL_UART_RxLineSta_INT_Dis(__UART__) CLEAR_BIT((__UART__)->IER, UART_IER_ELSI_Msk)
279 #define __LL_UART_TxHoldEmpyt_INT_En(__UART__) SET_BIT((__UART__)->IER, UART_IER_ETBEI_Msk)
286 #define __LL_UART_TxHoldEmpyt_INT_Dis(__UART__) CLEAR_BIT((__UART__)->IER, UART_IER_ETBEI_Msk)
293 #define __LL_UART_RxDatAvl_INT_En(__UART__) SET_BIT((__UART__)->IER, UART_IER_ERBFI_Msk)
300 #define __LL_UART_RxDatAvl_INT_Dis(__UART__) CLEAR_BIT((__UART__)->IER, UART_IER_ERBFI_Msk)
/bsp/ti/c28x/tms320f28379d/board/
A Dboard.c55 IER = 0x0000; in rt_hw_board_init()
88 IER |= M_INT14; in rt_hw_board_init()
89 IER |= M_INT1; in rt_hw_board_init()
/bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/
A Ddw_uart_ll.h280 __IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt enable register */ member
296 uart_base->IER |= (DW_UART_IER_ERBFI_EN | DW_UART_IER_ELSI_EN); in dw_uart_enable_recv_irq()
301 uart_base->IER &= ~(DW_UART_IER_ERBFI_EN | DW_UART_IER_ELSI_EN); in dw_uart_disable_recv_irq()
306 uart_base->IER |= DW_UART_IER_ETBEI_EN; in dw_uart_enable_trans_irq()
311 uart_base->IER &= ~(DW_UART_IER_ETBEI_EN); in dw_uart_disable_trans_irq()
383 return uart_base->IER; in dw_uart_get_intr_en_status()
388 uart_base->IER = status; in dw_uart_set_intr_en_status()

Completed in 106 milliseconds

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