1 #ifndef __DM9000_H__ 2 #define __DM9000_H__ 3 4 #define DM9000_IO_BASE 0x20000300 5 #define DM9000_DATA_BASE 0x20000304 6 7 #define DM9000_IO (*((volatile rt_uint16_t *) DM9000_IO_BASE)) // CMD = 0 8 #define DM9000_DATA (*((volatile rt_uint16_t *) DM9000_DATA_BASE)) // CMD = 1 9 10 #define DM9000_inb(r) (*(volatile rt_uint8_t *)r) 11 #define DM9000_outb(r, d) (*(volatile rt_uint8_t *)r = d) 12 #define DM9000_inw(r) (*(volatile rt_uint16_t *)r) 13 #define DM9000_outw(r, d) (*(volatile rt_uint16_t *)r = d) 14 15 #define DM9000_ID 0x90000A46 /* DM9000 ID */ 16 #define DM9000_PKT_MAX 1536 /* Received packet max size */ 17 #define DM9000_PKT_RDY 0x01 /* Packet ready to receive */ 18 19 #define DM9000_NCR 0x00 20 #define DM9000_NSR 0x01 21 #define DM9000_TCR 0x02 22 #define DM9000_TSR1 0x03 23 #define DM9000_TSR2 0x04 24 #define DM9000_RCR 0x05 25 #define DM9000_RSR 0x06 26 #define DM9000_ROCR 0x07 27 #define DM9000_BPTR 0x08 28 #define DM9000_FCTR 0x09 29 #define DM9000_FCR 0x0A 30 #define DM9000_EPCR 0x0B 31 #define DM9000_EPAR 0x0C 32 #define DM9000_EPDRL 0x0D 33 #define DM9000_EPDRH 0x0E 34 #define DM9000_WCR 0x0F 35 36 #define DM9000_PAR 0x10 37 #define DM9000_MAR 0x16 38 39 #define DM9000_GPCR 0x1e 40 #define DM9000_GPR 0x1f 41 #define DM9000_TRPAL 0x22 42 #define DM9000_TRPAH 0x23 43 #define DM9000_RWPAL 0x24 44 #define DM9000_RWPAH 0x25 45 46 #define DM9000_VIDL 0x28 47 #define DM9000_VIDH 0x29 48 #define DM9000_PIDL 0x2A 49 #define DM9000_PIDH 0x2B 50 51 #define DM9000_CHIPR 0x2C 52 #define DM9000_TCR2 0x2D 53 #define DM9000_OTCR 0x2E 54 #define DM9000_SMCR 0x2F 55 56 #define DM9000_ETCR 0x30 /* early transmit control/status register */ 57 #define DM9000_CSCR 0x31 /* check sum control register */ 58 #define DM9000_RCSSR 0x32 /* receive check sum status register */ 59 60 #define DM9000_MRCMDX 0xF0 61 #define DM9000_MRCMD 0xF2 62 #define DM9000_MRRL 0xF4 63 #define DM9000_MRRH 0xF5 64 #define DM9000_MWCMDX 0xF6 65 #define DM9000_MWCMD 0xF8 66 #define DM9000_MWRL 0xFA 67 #define DM9000_MWRH 0xFB 68 #define DM9000_TXPLL 0xFC 69 #define DM9000_TXPLH 0xFD 70 #define DM9000_ISR 0xFE 71 #define DM9000_IMR 0xFF 72 73 #define CHIPR_DM9000A 0x19 74 #define CHIPR_DM9000B 0x1B 75 76 #define NCR_EXT_PHY (1<<7) 77 #define NCR_WAKEEN (1<<6) 78 #define NCR_FCOL (1<<4) 79 #define NCR_FDX (1<<3) 80 #define NCR_LBK (3<<1) 81 #define NCR_RST (1<<0) 82 83 #define NSR_SPEED (1<<7) 84 #define NSR_LINKST (1<<6) 85 #define NSR_WAKEST (1<<5) 86 #define NSR_TX2END (1<<3) 87 #define NSR_TX1END (1<<2) 88 #define NSR_RXOV (1<<1) 89 90 #define TCR_TJDIS (1<<6) 91 #define TCR_EXCECM (1<<5) 92 #define TCR_PAD_DIS2 (1<<4) 93 #define TCR_CRC_DIS2 (1<<3) 94 #define TCR_PAD_DIS1 (1<<2) 95 #define TCR_CRC_DIS1 (1<<1) 96 #define TCR_TXREQ (1<<0) 97 98 #define TSR_TJTO (1<<7) 99 #define TSR_LC (1<<6) 100 #define TSR_NC (1<<5) 101 #define TSR_LCOL (1<<4) 102 #define TSR_COL (1<<3) 103 #define TSR_EC (1<<2) 104 105 #define RCR_WTDIS (1<<6) 106 #define RCR_DIS_LONG (1<<5) 107 #define RCR_DIS_CRC (1<<4) 108 #define RCR_ALL (1<<3) 109 #define RCR_RUNT (1<<2) 110 #define RCR_PRMSC (1<<1) 111 #define RCR_RXEN (1<<0) 112 113 #define RSR_RF (1<<7) 114 #define RSR_MF (1<<6) 115 #define RSR_LCS (1<<5) 116 #define RSR_RWTO (1<<4) 117 #define RSR_PLE (1<<3) 118 #define RSR_AE (1<<2) 119 #define RSR_CE (1<<1) 120 #define RSR_FOE (1<<0) 121 122 #define FCTR_HWOT(ot) (( ot & 0xf ) << 4 ) 123 #define FCTR_LWOT(ot) ( ot & 0xf ) 124 125 #define IMR_PAR (1<<7) 126 #define IMR_ROOM (1<<3) 127 #define IMR_ROM (1<<2) 128 #define IMR_PTM (1<<1) 129 #define IMR_PRM (1<<0) 130 131 #define ISR_ROOS (1<<3) 132 #define ISR_ROS (1<<2) 133 #define ISR_PTS (1<<1) 134 #define ISR_PRS (1<<0) 135 #define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS) 136 137 #define EPCR_REEP (1<<5) 138 #define EPCR_WEP (1<<4) 139 #define EPCR_EPOS (1<<3) 140 #define EPCR_ERPRR (1<<2) 141 #define EPCR_ERPRW (1<<1) 142 #define EPCR_ERRE (1<<0) 143 144 #define GPCR_GEP_CNTL (1<<0) 145 146 int rt_hw_dm9000_init(void); 147 148 #endif 149