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Searched refs:INTSTATUS (Results 1 – 25 of 36) sorted by relevance

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/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_dma_drv.h465 volatile uint32_t tmp = ptr->INTSTATUS; in dma_check_transfer_status()
473 ptr->INTSTATUS = tmp_channel; in dma_check_transfer_status()
478 ptr->INTSTATUS = tmp_channel; in dma_check_transfer_status()
483 ptr->INTSTATUS = tmp_channel; in dma_check_transfer_status()
500 …ptr->INTSTATUS = ((1 << (DMA_STATUS_TC_SHIFT + ch_index)) | (1 << (DMA_STATUS_ERROR_SHIFT + ch_ind… in dma_clear_transfer_status()
548 ptr->INTSTATUS = mask; /* Write-1-Clear */ in dma_clear_irq_status()
558 return ptr->INTSTATUS; in dma_get_irq_status()
/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_timer.c265 pReg->INTSTATUS = 0x1; in HAL_TIMER_ClrInt()
266 while (pReg->INTSTATUS && timeOut) { in HAL_TIMER_ClrInt()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_evsys_d51.h72 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; in hri_evsys_get_INTSTATUS_CHINT0_bit()
77 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; in hri_evsys_get_INTSTATUS_CHINT1_bit()
82 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; in hri_evsys_get_INTSTATUS_CHINT2_bit()
87 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; in hri_evsys_get_INTSTATUS_CHINT3_bit()
92 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; in hri_evsys_get_INTSTATUS_CHINT4_bit()
97 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; in hri_evsys_get_INTSTATUS_CHINT5_bit()
102 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; in hri_evsys_get_INTSTATUS_CHINT6_bit()
107 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; in hri_evsys_get_INTSTATUS_CHINT7_bit()
112 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; in hri_evsys_get_INTSTATUS_CHINT8_bit()
134 tmp = ((Evsys *)hw)->INTSTATUS.reg; in hri_evsys_get_INTSTATUS_reg()
[all …]
A Dhri_dmac_d51.h90 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; in hri_dmac_get_INTSTATUS_CHINT0_bit()
95 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; in hri_dmac_get_INTSTATUS_CHINT1_bit()
100 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; in hri_dmac_get_INTSTATUS_CHINT2_bit()
105 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; in hri_dmac_get_INTSTATUS_CHINT3_bit()
110 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; in hri_dmac_get_INTSTATUS_CHINT4_bit()
115 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; in hri_dmac_get_INTSTATUS_CHINT5_bit()
120 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; in hri_dmac_get_INTSTATUS_CHINT6_bit()
125 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; in hri_dmac_get_INTSTATUS_CHINT7_bit()
130 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; in hri_dmac_get_INTSTATUS_CHINT8_bit()
251 tmp = ((Dmac *)hw)->INTSTATUS.reg; in hri_dmac_get_INTSTATUS_reg()
[all …]
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_evsys_d51.h72 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; in hri_evsys_get_INTSTATUS_CHINT0_bit()
77 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; in hri_evsys_get_INTSTATUS_CHINT1_bit()
82 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; in hri_evsys_get_INTSTATUS_CHINT2_bit()
87 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; in hri_evsys_get_INTSTATUS_CHINT3_bit()
92 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; in hri_evsys_get_INTSTATUS_CHINT4_bit()
97 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; in hri_evsys_get_INTSTATUS_CHINT5_bit()
102 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; in hri_evsys_get_INTSTATUS_CHINT6_bit()
107 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; in hri_evsys_get_INTSTATUS_CHINT7_bit()
112 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; in hri_evsys_get_INTSTATUS_CHINT8_bit()
134 tmp = ((Evsys *)hw)->INTSTATUS.reg; in hri_evsys_get_INTSTATUS_reg()
[all …]
A Dhri_dmac_d51.h90 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; in hri_dmac_get_INTSTATUS_CHINT0_bit()
95 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; in hri_dmac_get_INTSTATUS_CHINT1_bit()
100 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; in hri_dmac_get_INTSTATUS_CHINT2_bit()
105 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; in hri_dmac_get_INTSTATUS_CHINT3_bit()
110 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; in hri_dmac_get_INTSTATUS_CHINT4_bit()
115 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; in hri_dmac_get_INTSTATUS_CHINT5_bit()
120 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; in hri_dmac_get_INTSTATUS_CHINT6_bit()
125 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; in hri_dmac_get_INTSTATUS_CHINT7_bit()
130 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; in hri_dmac_get_INTSTATUS_CHINT8_bit()
251 tmp = ((Dmac *)hw)->INTSTATUS.reg; in hri_dmac_get_INTSTATUS_reg()
[all …]
/bsp/microchip/same54/bsp/hri/
A Dhri_evsys_e54.h72 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; in hri_evsys_get_INTSTATUS_CHINT0_bit()
77 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; in hri_evsys_get_INTSTATUS_CHINT1_bit()
82 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; in hri_evsys_get_INTSTATUS_CHINT2_bit()
87 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; in hri_evsys_get_INTSTATUS_CHINT3_bit()
92 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; in hri_evsys_get_INTSTATUS_CHINT4_bit()
97 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; in hri_evsys_get_INTSTATUS_CHINT5_bit()
102 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; in hri_evsys_get_INTSTATUS_CHINT6_bit()
107 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; in hri_evsys_get_INTSTATUS_CHINT7_bit()
112 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; in hri_evsys_get_INTSTATUS_CHINT8_bit()
134 tmp = ((Evsys *)hw)->INTSTATUS.reg; in hri_evsys_get_INTSTATUS_reg()
[all …]
A Dhri_dmac_e54.h90 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; in hri_dmac_get_INTSTATUS_CHINT0_bit()
95 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; in hri_dmac_get_INTSTATUS_CHINT1_bit()
100 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; in hri_dmac_get_INTSTATUS_CHINT2_bit()
105 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; in hri_dmac_get_INTSTATUS_CHINT3_bit()
110 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; in hri_dmac_get_INTSTATUS_CHINT4_bit()
115 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; in hri_dmac_get_INTSTATUS_CHINT5_bit()
120 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; in hri_dmac_get_INTSTATUS_CHINT6_bit()
125 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; in hri_dmac_get_INTSTATUS_CHINT7_bit()
130 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; in hri_dmac_get_INTSTATUS_CHINT8_bit()
251 tmp = ((Dmac *)hw)->INTSTATUS.reg; in hri_dmac_get_INTSTATUS_reg()
[all …]
/bsp/ck802/libraries/common/gpio/
A Ddw_gpio.h42 … __IM uint32_t INTSTATUS; /* Offset: 0x010 (R) Interrupt status of Port */ member
A Ddw_gpio.c218 uint32_t value = gpio_control_reg->INTSTATUS; in dw_gpio_irqhandler()
/bsp/thead-smart/drivers/
A Ddw_gpio.h36 … __IM uint32_t INTSTATUS; /* Offset: 0x010 (R) Interrupt status of Port */ member
A Ddw_gpio.c250 uint32_t value = gpio_control_reg->INTSTATUS; in dw_gpio_irqhandler()
/bsp/microchip/samc21/bsp/hri/
A Dhri_dmac_c21.h262 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; in hri_dmac_get_INTSTATUS_CHINT0_bit()
267 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; in hri_dmac_get_INTSTATUS_CHINT1_bit()
272 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; in hri_dmac_get_INTSTATUS_CHINT2_bit()
277 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; in hri_dmac_get_INTSTATUS_CHINT3_bit()
282 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; in hri_dmac_get_INTSTATUS_CHINT4_bit()
287 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; in hri_dmac_get_INTSTATUS_CHINT5_bit()
292 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; in hri_dmac_get_INTSTATUS_CHINT6_bit()
297 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; in hri_dmac_get_INTSTATUS_CHINT7_bit()
302 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; in hri_dmac_get_INTSTATUS_CHINT8_bit()
323 tmp = ((Dmac *)hw)->INTSTATUS.reg; in hri_dmac_get_INTSTATUS_reg()
[all …]
/bsp/hpmicro/libraries/hpm_sdk/drivers/src/
A Dhpm_dma_drv.c38 …ptr->INTSTATUS = (DMA_INTSTATUS_TC_SET(1) | DMA_INTSTATUS_ABORT_SET(1) | DMA_INTSTATUS_ERROR_SET(1… in dma_setup_channel()
/bsp/microchip/saml10/bsp/hri/
A Dhri_dmac_l10.h262 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0_Msk) >> DMAC_INTSTATUS_CHINT0_Pos; in hri_dmac_get_INTSTATUS_CHINT0_bit()
267 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1_Msk) >> DMAC_INTSTATUS_CHINT1_Pos; in hri_dmac_get_INTSTATUS_CHINT1_bit()
272 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2_Msk) >> DMAC_INTSTATUS_CHINT2_Pos; in hri_dmac_get_INTSTATUS_CHINT2_bit()
277 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3_Msk) >> DMAC_INTSTATUS_CHINT3_Pos; in hri_dmac_get_INTSTATUS_CHINT3_bit()
282 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4_Msk) >> DMAC_INTSTATUS_CHINT4_Pos; in hri_dmac_get_INTSTATUS_CHINT4_bit()
287 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5_Msk) >> DMAC_INTSTATUS_CHINT5_Pos; in hri_dmac_get_INTSTATUS_CHINT5_bit()
292 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6_Msk) >> DMAC_INTSTATUS_CHINT6_Pos; in hri_dmac_get_INTSTATUS_CHINT6_bit()
297 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7_Msk) >> DMAC_INTSTATUS_CHINT7_Pos; in hri_dmac_get_INTSTATUS_CHINT7_bit()
303 tmp = ((Dmac *)hw)->INTSTATUS.reg; in hri_dmac_get_INTSTATUS_reg()
310 return ((Dmac *)hw)->INTSTATUS.reg; in hri_dmac_read_INTSTATUS_reg()
A Dhri_evsys_l10.h169 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0_Msk) >> EVSYS_INTSTATUS_CHINT0_Pos; in hri_evsys_get_INTSTATUS_CHINT0_bit()
174 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1_Msk) >> EVSYS_INTSTATUS_CHINT1_Pos; in hri_evsys_get_INTSTATUS_CHINT1_bit()
179 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2_Msk) >> EVSYS_INTSTATUS_CHINT2_Pos; in hri_evsys_get_INTSTATUS_CHINT2_bit()
184 return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3_Msk) >> EVSYS_INTSTATUS_CHINT3_Pos; in hri_evsys_get_INTSTATUS_CHINT3_bit()
191 tmp = ((Evsys *)hw)->INTSTATUS.reg; in hri_evsys_get_INTSTATUS_reg()
198 return ((Evsys *)hw)->INTSTATUS.reg; in hri_evsys_read_INTSTATUS_reg()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/
A Dhpm_dma_regs.h19 __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/
A Dhpm_dma_regs.h21 __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ member
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/
A Dhpm_dma_regs.h19 __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ member
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Devsys.h577 __I EVSYS_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x014 (R/ 32) Interrupt Status */ member
/bsp/microchip/same54/bsp/include/component/
A Devsys.h577 __I EVSYS_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x014 (R/ 32) Interrupt Status */ member
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Devsys.h577 __I EVSYS_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x014 (R/ 32) Interrupt Status */ member
/bsp/acm32/acm32f0x0-nucleo/libraries/Device/
A DACM32F0x0.h131 __IO uint32_t INTSTATUS; // 0x18 member
/bsp/microchip/saml10/bsp/include/component/
A Devsys.h905 …__I EVSYS_INTSTATUS_Type INTSTATUS; /**< Offset: 0x14 (R/ 32) Interrupt Status */ member
/bsp/acm32/acm32f4xx-nucleo/libraries/Device/
A DACM32F4.h153 __IO uint32_t INTSTATUS; member

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