1 /**************************************************************************//** 2 * 3 * @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 * 7 * Change Logs: 8 * Date Author Notes 9 * 2020-1-16 Wayne First version 10 * 11 ******************************************************************************/ 12 13 #ifndef __ACODEC_NAU88L25_H__ 14 #define __ACODEC_NAU88L25_H__ 15 16 #include <rtdevice.h> 17 18 enum 19 { 20 REG_SOFTWARE_RST, 21 REG_ENA_CTRL, 22 REG_I2C_ADDR_SET, 23 REG_CLK_DIVIDER, 24 REG_FLL1, 25 REG_FLL2, 26 REG_FLL3, 27 REG_FLL4, 28 REG_FLL5, 29 REG_FLL6, 30 REG_FLL_VCO_RSV, 31 REG_HSD_CTRL = 0xC, //0xC 32 REG_JACK_DET_CTRL, 33 REG_INTERRUPT_MASK = 0xF, //0xF 34 REG_IRQ_STATUS, 35 REG_INT_LCR_KEY_STATUS, 36 REG_INTERRUPT_DIS_CTRL, 37 REG_SAR_CTRL, 38 REG_KEYDET_CTRL, 39 REG_VDET_THRESHOLD_1, 40 REG_VDET_THRESHOLD_2, 41 REG_VDET_THRESHOLD_3, 42 REG_VDET_THRESHOLD_4, 43 REG_GPIO34_CTRL, 44 REG_GPIO12_CTRL, 45 REG_TDM_CTRL, 46 REG_I2S_PCM_CTRL1, 47 REG_I2S_PCM_CTRL2, 48 REG_LEFT_TIME_SLOT, 49 REG_RIGHT_TIME_SLOT, 50 REG_BIQ_CTRL, 51 REG_BIQ_COF1, 52 REG_BIQ_COF2, 53 REG_BIQ_COF3, 54 REG_BIQ_COF4, 55 REG_BIQ_COF5, 56 REG_BIQ_COF6, 57 REG_BIQ_COF7, 58 REG_BIQ_COF8, 59 REG_BIQ_COF9, //29 60 REG_BIQ_COF10, 61 REG_ADC_RATE, 62 REG_DAC_CTRL1, 63 REG_DAC_CTRL2, 64 REG_DAC_DGAIN_CTRL = 0x2F, 65 REG_ADC_DGAIN_CTRL, 66 REG_MUTE_CTRL, 67 REG_HSVOL_CTRL, 68 REG_DACL_CTRL, 69 REG_DACR_CTRL, 70 REG_ADC_DRC_KNEE_IP12 = 0x38, 71 REG_ADC_DRC_KNEE_IP34, 72 REG_ADC_DRC_SLOPES, 73 REG_ADC_DRC_ATKDCY, 74 REG_DAC_DRC_KNEE_IP12 = 0x45, //0x45 75 REG_DAC_DRC_KNEE_IP34, 76 REG_DAC_DRC_SLOPES, 77 REG_DAC_DRC_ATKDCY = 0x48, //0x48 78 REG_MODE_CTRL = 0x4C, //0x4C 79 REG_CLASSG_CTRL = 0x50, //0x50 80 REG_OPT_EFUSE_CTRL, 81 REG_MISC_CTRL = 0x55, //0x55 82 83 REG_I2C_DEVICE_ID = 0x58, //0x58 84 REG_SARDOUT_RAM_STATUS, 85 86 REG_BIAS_ADJ = 0x66, //0x66 87 88 REG_TRIM_SETTINGS = 0x68, //0x68 89 REG_ANALOG_CONTROL_1, 90 REG_ANALOG_CONTROL_2, 91 92 REG_ANALOG_ADC_1 = 0x71, //0x71 93 REG_ANALOG_ADC_2, 94 REG_RDAC, 95 REG_MIC_BIAS, //0x74 96 REG_BOOST = 0x76, 97 REG_FEPGA, 98 REG_POWER_UP_CONTROL = 0x7F, //0x7F 99 REG_CHARGE_PUMP_AND_DOWN_CONTROL, //0x80 100 REG_CHARGE_PUMP_INPUT_READ, 101 REG_GENERAL_STATUS 102 }; 103 104 105 // R1 REG_ENA_CTRL 106 107 #define CLK_DRC_EN (1) 108 #define CLK_SAR_EN (1 << 1) 109 #define CLK_BIST_EN (1 << 3) 110 #define CLK_I2S_EN (1 << 4) 111 #define CLK_MODE_EN (1 << 5) 112 #define DCLK_DAC_EN (1 << 6) 113 #define DCLK_ADC_EN (1 << 7) 114 #define ADC_EN (1 << 8) 115 #define LDAC_EN (1 << 9) 116 #define RDAC_EN (1 << 10) 117 #define CLK_DAC_INV (1 << 14) 118 #define CMLCK_ENB (1 << 15) 119 120 121 // R2 REG_I2C_ADDR_SET 122 #define I2C_ADDDR_SEL 123 #define I2C_LSB_VAL_IO 124 125 126 // R3 REG_CLK_DIVIDER 127 #define MCLK_SRC_DIV1 (0) 128 #define MCLK_SRC_INVERTED (1) 129 #define MCLK_SRC_DIV2 (2) 130 #define MCLK_SRC_DIV4 (3) 131 #define MCLK_SRC_DIV8 (4) 132 #define MCLK_SRC_DIV16 (5) 133 #define MCLK_SRC_DIV32 (6) 134 #define MCLK_SRC_DIV3 (7) 135 #define MCLK_SRC_DIV6 (10) 136 #define MCLK_SRC_DIV12 (11) 137 #define MCLK_SRC_DIV24 (12) 138 #define MCLK_SRC_DIV48 (13) 139 #define MCLK_SRC_DIV96 (14) 140 #define MCLK_SRC_DIV5 (15) 141 142 #define CLK_DAC_SRC_DIV1 (0) 143 #define CLK_DAC_SRC_DIV2 (1 << 4) 144 #define CLK_DAC_SRC_DIV4 (2 << 4) 145 #define CLK_DAC_SRC_DIV8 (3 << 4) 146 147 #define CLK_ADC_SRC_DIV1 (0) 148 #define CLK_ADC_SRC_DIV2 (1 << 6) 149 #define CLK_ADC_SRC_DIV4 (2 << 6) 150 #define CLK_ADC_SRC_DIV8 (3 << 6) 151 152 #define CLK_ADC_PL_INVERT (1 << 10) 153 #define CLK_DAC_PL_INVERT (1 << 11) 154 #define CLK_CODEC_SRC_IMCLK (0) 155 #define CLK_CODEC_SRC_PIN (1 << 13) 156 #define CLK_SYSCLK_SRC_VCO (1 << 15) 157 #define CLK_SYSCLK_SRC_PIN (0) 158 159 // R4 REG_FLL1 160 #define FLL_RATIO_512K (1) 161 #define FLL_RATIO_256K (1 << 1) 162 #define FLL_RATIO_128K (1 << 2) 163 #define FLL_RATIO_64K (1 << 3) 164 #define FLL_RATIO_32K (1 << 4) 165 #define FLL_RATIO_8K (1 << 5) 166 #define FLL_RATIO_4K (1 << 6) 167 #define FLL_LCOK_BP (1 << 7) 168 #define ICTRL_V2I_AMP2X (1 << 8) 169 #define ICTRL_V2I_AMP (1 << 9) 170 #define ICTRL_V2I_BOTHAMP (3 << 8) 171 #define ICTRL_LATCH_1X (1 << 10) 172 #define ICTRL_LATCH_2X (3 << 10) 173 #define ICTRL_LATCH_3X (7 << 10) 174 #define FLL1SELDAC_POS (13) 175 #define FLL1SELDAC_MSK (0x7 << FLL1SELDAC_POS) 176 177 // R5 REG_FLL2 178 #define FLLFRAC_POS (0) 179 #define FLLFRAC_MSK (0xFFFF << FLLFRAC_POS) 180 181 // R6 REG_FLL3 182 #define FLL_INTEGER(x) (x << 0) 183 #define FLL_CLK_REF_SRC_MCLKPIN (0) 184 #define FLL_CLK_REF_SRC_BCLKPIN (1 << 11) 185 #define FLL_CLK_REF_SRC_FSPIN (0x3 << 10) 186 #define GAIN_ERR_x1 (0x0) 187 #define GAIN_ERR_x2 (0x1 << 12) 188 #define GAIN_ERR_x4 (0x2 << 12) 189 #define GAIN_ERR_x8 (0x3 << 12) 190 #define GAIN_ERR_x16 (0x4 << 12) 191 #define GAIN_ERR_x32 (0x5 << 12) 192 #define GAIN_ERR_x64 (0x6 << 12) 193 194 195 // R7 REG_FLL4 196 #define FLL_N2(x) (x << 0) 197 #define FLL_CLK_REF_DIV1 (0x0 << 10) 198 #define FLL_CLK_REF_DIV2 (0x1 << 10) 199 #define FLL_CLK_REF_DIV4 (0x2 << 10) 200 #define FLL_CLK_REF_DIV8 (0x3 << 10) 201 #define FLL_CLK_REF_DIV_4CHK_1 (0x0 << 12) 202 #define FLL_CLK_REF_DIV_4CHK_1_2 (0x1 << 12) 203 #define FLL_CLK_REF_DIV_4CHK_1_4 (0x2 << 12) 204 #define FLL_CLK_REF_DIV_4CHK_1_8 (0x3 << 12) 205 #define FLL_CLK_REF_DIV_4CHK_1_16 (0x4 << 12) 206 #define FLL_CLK_REF_DIV_4CHK_1_32 (0x5 << 12) 207 208 209 // R8 REG_FLL5 210 #define FLL_LOCK_LENGTH(x) (x << 0) 211 #define FILTER_SW (0x1 << 12) 212 #define CLK_FILTER_SW (0x1 << 13) 213 #define CHB_FILTER_EN (0x1 << 14) 214 #define PDB_DACICTRL (0x1 << 15) 215 216 217 // R9 REG_FLL6 218 #define FLL_SD_DITHER_SEL_1LSB (0x1 << 4) 219 #define FLL_SD_DITHER_SEL_2LSBs (0x2 << 4) 220 #define FLL_SD_DITHER_SEL_3LSBs (0x3 << 4) 221 #define FLL_FLTR_DITHER_SEL_1LSB (0x1 << 6) 222 #define FLL_FLTR_DITHER_SEL_2LSBs (0x2 << 6) 223 #define FLL_FLTR_DITHER_SEL_3LSBs (0x3 << 6) 224 #define CUTOFF600 (0x1 << 12) 225 #define CUTOFF500 (0x1 << 13) 226 #define SDM_EN (0x1 << 14) 227 #define DCO_EN (0x1 << 15) 228 229 230 231 // R A REG_FLL_VCO_RSV 232 #define DOUT2VCO_RSV_POS (0) 233 #define DOUT2VCO_RSV_Msk (0xFFFF << FLLFRAC_POS) 234 235 // R C REG_HSD_CTRL 236 #define MANU_SPKR_DWN1L_OPEN (0) 237 #define MANU_SPKR_DWN1L_GND (1) 238 #define MANU_SPKR_DWN1R_OPEN (0) 239 #define MANU_SPKR_DWN1R_GND (1 << 1) 240 #define MANU_ENGND2_OPEN (0) 241 #define MANU_ENGND2_GND (1 << 2) 242 #define MANU_ENGND1_OPEN (0) 243 #define MANU_ENGND1_GND (1 << 3) 244 #define MANUAL_START (1 << 4) 245 #define HSD_AUTO_MODE (1 << 6) 246 #define RESET_HSD (1 << 15) 247 248 249 // R D REG_JACK_DET_CTRL 250 #define JKDET_LOGIC_AND_GATE (1) 251 #define JKDET_LOGIC_OR_GATE (0) 252 #define JKDET_PL_N_INVERT (1) 253 #define JKDET_PL_INVERT (0) 254 #define EJECT_DT(x) (x << 2) 255 #define INSERT_DT(x) (x << 5) 256 #define DB_BP_MODE_BYBASS_DEBOUNCE (1 << 8) 257 #define DB_BP_MODE_NORMAL (0) 258 #define JD_RESTART (1) 259 #define JK_1_PL_GPIO2JD1 (0) 260 #define JK_1_PL_GPIO2JD1_INV (1 << 10) 261 #define JK_1_PL_IGNORE_0 (2 << 10) 262 #define JK_1_PL_IGNORE_1 (3 << 10) 263 #define JK_2_PL_JKDETL (0) 264 #define JK_2_PL_JKDETL_INV (1 << 12) 265 #define JK_2_PL_IGNORE_0 (2 << 12) 266 #define JK_2_PL_IGNORE_1 (3 << 12) 267 #define JK_3_PL_GPIO3JD2 (0) 268 #define JK_3_PL_GPIO3JD2_INV (1 << 14) 269 #define JK_3_PL_IGNORE_0 (2 << 14) 270 #define JK_3_PL_IGNORE_1 (3 << 14) 271 272 273 // R F REG_INTERRUPT_MASK 274 #define JK_DET_INTP_MASK (1) 275 #define JK_EJECT_INTP_MASK (1 << 2) 276 #define MIC_DET_INTP_MASK (1 << 4) 277 #define SHORT_KEY_INTP_MASK (1 << 5) 278 #define LONG_KEYINTP_MASK (1 << 6) 279 #define KEY_RELEASE_INTP_MASK (1 << 7) 280 #define RMS_INTP_MASK (1 << 8) 281 #define APR_EMRGENCY_SHTDWN1_INTP_MASK (1 << 9) 282 #define HSD_COMPLETE_INTP_MASK (1 << 10) 283 #define IRQ_OE (1 << 11) 284 #define IRQ_DS (1 << 12) 285 #define IRQ_PE (1 << 13) 286 #define IRQ_PS (1 << 14) 287 #define IRQ_PL (1 << 15) 288 289 290 // R 10 291 #define JACK_DET_IRQ_JACK_INSERT (1) 292 #define JACK_DET_IRQ_JACK_INSERT_REMOVED (2) 293 #define JACK_EJCT_IRQ_JACK_INSERT (1 << 2) 294 #define JACK_EJCT_IRQ_JACK_INSERT_REMOVED (2 << 2) 295 296 #define MIC_DET_INT (1 << 4) 297 #define SHORT_KEY_INT (1 << 5) 298 #define LONG_KEY_INT (1 << 6) 299 #define KEY_RELEASE_INT (1 << 7) 300 #define RMS_INT (1 << 8) 301 #define APR_EMRG_SHTDWN (1 << 9) 302 #define HSD_COMPL_ETE_INT (1 << 10) 303 304 305 // R 11 306 #define NT_CLR_KEY_STATUS_LK0 (1) 307 #define NT_CLR_KEY_STATUS_LK1 (1 << 1) 308 #define NT_CLR_KEY_STATUS_LK2 (1 << 2) 309 #define NT_CLR_KEY_STATUS_LK3 (1 << 3) 310 #define NT_CLR_KEY_STATUS_LK4 (1 << 4) 311 #define NT_CLR_KEY_STATUS_LK5 (1 << 5) 312 #define NT_CLR_KEY_STATUS_LK6 (1 << 6) 313 #define NT_CLR_KEY_STATUS_LK7 (1 << 7) 314 315 #define NT_CLR_KEY_STATUS_SK0 (1 << 8) 316 #define NT_CLR_KEY_STATUS_SK1 (1 << 9) 317 #define NT_CLR_KEY_STATUS_SK2 (1 << 10) 318 #define NT_CLR_KEY_STATUS_SK3 (1 << 11) 319 #define NT_CLR_KEY_STATUS_SK4 (1 << 12) 320 #define NT_CLR_KEY_STATUS_SK5 (1 << 13) 321 #define NT_CLR_KEY_STATUS_SK6 (1 << 14) 322 #define NT_CLR_KEY_STATUS_SK7 (1 << 15) 323 324 325 // R 12 326 #define JACK_DET_INT_DIS (1) 327 #define JACK_EJCT_INT_DIS (1 << 2) 328 #define MIC_DET_INT_DIS (1 << 4) 329 #define SHORT_KEY_INT_DIS (1 << 5) 330 #define LONG_KEY_INT_DIS (1 << 6) 331 #define KEY_RELEASE_INT_DIS (1 << 7) 332 #define RMS_INT_DIS (1 << 8) 333 #define SHRT_SHTD_MIN_INT_DIS (1 << 9) 334 #define HSD_COMPL_ETE_INT_DIS (1 << 10) 335 #define LONG_KEY0_INT_DIS (1 << 11) 336 #define KEY0_RELEASE_INT_DIS (1 << 12) 337 #define KEY_RELEASE_CLR_INTR (1 << 13) 338 339 340 // R 13 SAR_CTRL 341 #define SAMPLE_SPEED_500NS (0) 342 #define SAMPLE_SPEED_4US (1 << 0) 343 #define SAMPLE_SPEED_8US (2 << 0) 344 #define SAMPLE_SPEED_16US (3 << 0) 345 #define COMP_SPEED_500NS (0 << 2) 346 #define COMP_SPEED_1US (1 << 2) 347 #define COMP_SPEED_2US (2 << 2) 348 #define COMP_SPEED_4US (3 << 2) 349 #define RES_SEL_35K_OHMS (0) 350 #define RES_SEL_70K_OHMS (1 << 4) 351 #define RES_SEL_170K_OHMS (2 << 4) 352 #define RES_SEL_360K_OHMS (3 << 4) 353 #define HV_SEL_VDDMIC (1 << 7) 354 #define HV_SEL_NCIBIAS (0) 355 #define SAR_TRACKGAIN_POS (8) 356 #define SAR_TRACKGAIN_MSK (0x7 << SAR_TRACKGAIN_POS) 357 #define INPUT_SEL_JKSLV (1 << 11) 358 #define INPUT_JKR2 (0) 359 #define SAR_ENA (1 << 12) 360 #define SAR_OUT_INV (1 << 13) 361 362 363 // R 14 364 #define HY_COEFF(x) (x << 0) 365 #define SARADC_VDET_COEFF(x) (x << 4) 366 367 368 #define ENABLE_LEVEL_KEY0 (0) 369 #define ENABLE_LEVEL_KEY1 (1 << 8) 370 #define ENABLE_LEVEL_KEY2 (2 << 8) 371 #define ENABLE_LEVEL_KEY3 (3 << 8) 372 #define ENABLE_LEVEL_KEY4 (4 << 8) 373 #define ENABLE_LEVEL_KEY5 (5 << 8) 374 #define ENABLE_LEVEL_KEY6 (6 << 8) 375 #define ENABLE_LEVEL_KEY7 (7 << 8) 376 377 #define SHORTKEY_DT_30MS (0) 378 #define SHORTKEY_DT_50MS (1 << 12) 379 #define SHORTKEY_DT_100MS (2 << 13) 380 381 #define LONGKEY_DT_500MS (0) 382 #define LONGKEY_DT_1S (1 << 14) 383 384 385 // R 15/16/17/18 386 #define SARADC_VDET_THR_1357_POS (0) 387 #define SARADC_VDET_THR_1357_MSK (0xFF << SARADC_VDET_THR_1357_POS) 388 389 #define SARADC_VDET_THR_0246_POS (8) 390 #define SARADC_VDET_THR_0246_MSK (0xFF << SARADC_VDET_THR_0246_POS) 391 392 393 // R 19 REG_GPIO34_CTRL 394 #define GPIO3_OE (1 << 0) 395 #define GPIO3_DS (1 << 1) 396 #define GPIO3_PS (1 << 2) 397 #define GPIO3_PE (1 << 3) 398 #define GPIO3O (1 << 4) 399 #define GPIO4_OE (1 << 7) 400 #define GPIO4_DS (1 << 8) 401 #define GPIO4_PS (1 << 9) 402 #define GPIO4_PE (1 << 10) 403 404 405 // R 1A REG_GPIO12_CTRL 406 #define GPIO1_OE (1 << 0) 407 #define GPIO1_PE (1 << 1) 408 #define GPIO1_DS (1 << 2) 409 #define GPIO1_PS (1 << 3) 410 #define GPIO1SEL(x) (x << 4) 411 #define GPIO1POL (1 << 7) 412 #define GPIO2_OE (1 << 8) 413 #define GPIO2_PE (1 << 9) 414 #define GPIO2_DS (1 << 10) 415 #define GPIO2_PS (1 << 11) 416 417 418 419 // R 1B REG_TDM_CTRL 420 #define ADC_TX_SEL_SLOT(x) (x << 0) 421 #define DAC_RIGHT_SEL_SLOT(x) (x << 4) 422 #define DAC_LEFT_SEL_SLOT(x) (x << 6) 423 #define PCM_OFFSET_MODE_CTRL (1 << 14) 424 #define TDM (1 << 15) 425 426 427 // R 1C REG_I2S_PCM_CTRL1 428 #define AIFMT0_RIGHTJUST (0) 429 #define AIFMT0_LEFTJUST (1 << 0) 430 #define AIFMT0_STANDI2S (2 << 0) 431 #define AIFMT0_PCMA_B (3 << 0) 432 433 #define WLEN0_16BIT (0) 434 #define WLEN0_20BIT (1 << 2) 435 #define WLEN0_24BIT (2 << 2) 436 #define WLEN0_32BIT (3 << 2) 437 438 #define ADCPHS0_LEFT (0) 439 #define ADCPHS0_RIGHT (1 << 4) 440 441 #define DACPHS0_LEFT (0) 442 #define DACPHS0_RIGHT (1 << 5) 443 444 #define LRP0 (1 << 6) 445 #define BCP0 (1 << 7) 446 #define UA_OFFSET_1S (0) 447 #define UA_OFFSET_2S (1) 448 #define CMB8_0_NORMAL (0) 449 #define CNB8_0_8BIT (1 << 10) 450 #define ADDAP0 (1 << 11) 451 #define ADCCM0_ULAW (2 << 12) 452 #define ADCCM0_ALAW (3 << 12) 453 #define DACCM0_ULAW (2 << 14) 454 #define DACCM0_ALAW (3 << 14) 455 456 457 458 // R 1D REG_2S_PCM_CTRL2 459 #define BLCKDIV_DIV2 (0) 460 #define BLCKDIV_DIV4 (1) 461 #define BLCKDIV_DIV8 (2) 462 #define BLCKDIV_DIV16 (3) 463 #define BLCKDIV_DIV32 (4) 464 #define BLCKDIV_DIV64 (5) 465 466 #define MS0_SLAVE (0) 467 #define MS0_MASTER (1 << 3) 468 469 #define ADCDAT0_OE (1 << 4) 470 #define ADCDAT0_PS_PULLUP (1 << 5) 471 #define ADCDAT0_PS_PULLDOWN (0) 472 473 #define ADCDAT0_PE (1 << 6) 474 #define PCM8BIT0 (1 << 8) 475 #define TRI0 (1 << 9) 476 #define PCM_TS_EN0 (1 << 10) 477 #define LRC_DIV_DIV256 (0) 478 #define LRC_DIV_DIV128 (1 << 12) 479 #define LRC_DIV_DIV64 (2 << 12) 480 #define LRC_DIV_DIV32 (3 << 12) 481 #define I2S_DRV (1 << 14) 482 #define I2S_TRI (1 << 15) 483 484 485 // R 1E REG_LEFT_TIME_SLOT 486 #define TSLOT_L0_POS (0) 487 #define TSLOT_L0_MSK (0x3FF << TSLOT_L0_POS) 488 #define DIS_FS_SHORT_DET (1 << 13) 489 #define FS_ERR_CMP_SEL_252MCLK (0) 490 #define FS_ERR_CMP_SEL_253MCLK (1 << 14) 491 #define FS_ERR_CMP_SEL_254MCLK (2 << 14) 492 #define FS_ERR_CMP_SEL_255MCLK (3 << 15) 493 494 495 // R 1F REG_RIGHT_TIME_SLOT 496 #define TSLOT_R0_POS (0) 497 #define TSLOT_R0_MSK (0x3FF << TSLOT_R0_POS) 498 499 500 // R 20 REG_BIQ_CTRL 501 #define BIQ_PATH_SE_ADC (0) 502 #define BIQ_PATH_SE_DAC (1) 503 #define BIQ_COF_SE_SYNC_FS (0) 504 #define BIQ_COF_SE_NO_SYNC (1 << 1) 505 #define ADC_PATH_EN (1 << 2) 506 #define DAC_PATH_EN (1 << 3) 507 #define BIQ_WRT_EN (1 << 4) 508 509 510 // R 21 REG_BIQ_COF1 511 #define BIQ_A1_L_POS (0) 512 #define BIQ_A1_L_MSK (0xFFFF << BIQ_A1_L_POS) 513 514 // R 22 REG_BIQ_COF2 515 #define BIQ_A1_H_POS (0) 516 #define BIQ_A1_H_MSK (0x7 << BIQ_A1_H_POS) 517 518 // R 23 REG_BIQ_COF3 519 #define BIQ_A2_L_POS (0) 520 #define BIQ_A2_L_MSK (0xFFFF << BIQ_A2_L_POS) 521 522 // R 24 REG_BIQ_COF4 523 #define BIQ_A2_H_POS (0) 524 #define BIQ_A2_H_MSK (0x7 << BIQ_A2_H_POS) 525 526 527 // R 25 REG_BIQ_COF5 528 #define BIQ_B0_L_POS (0) 529 #define BIQ_B0_L_MSK (0xFFFF << BIQ_B0_L_POS) 530 531 // R 26 REG_BIQ_COF6 532 #define BIQ_B0_H_POS (0) 533 #define BIQ_B0_H_MSK (0x7 << BIQ_B0_H_POS) 534 535 536 // R 27 REG_BIQ_COF7 537 #define BIQ_B1_L_POS (0) 538 #define BIQ_B1_L_MSK (0xFFFF << BIQ_B1_L_POS) 539 540 // R 28 REG_BIQ_COF8 541 #define BIQ_B1_H_POS (0) 542 #define BIQ_B1_H_MSK (0x7 << BIQ_B1_H_POS) 543 544 545 // R 29 REG_BIQ_COF9 546 #define BIQ_B2_L_POS (0) 547 #define BIQ_B2_L_MSK (0xFFFF << BIQ_B2_L_POS) 548 549 // R 2A REG_BIQ_COF10 550 #define BIQ_B2_H_POS (0) 551 #define BIQ_B2_H_MSK (0x7 << BIQ_B2_H_POS) 552 553 554 // R 2B REG_ADC_RATE 555 #define ADC_RATE_32 (0) 556 #define ADC_RATE_64 (1) 557 #define ADC_RATE_128 (2) 558 #define ADC_RATE_256 (3) 559 560 #define SMPL_RATE_48K (0) 561 #define SMPL_RATE_32K (1 << 5) 562 #define SMPL_RATE_96K (3 << 5) 563 #define SMPL_RATE_192K (7 << 5) 564 565 566 // R 2C REG_DAC_CTRL1 567 #define DAC_RATE_64 (0) 568 #define DAC_RATE_256 (1) 569 #define DAC_RATE_128 (2) 570 #define DAC_RATE_32 (4) 571 #define CUC_GAIN_ADJ(x) (x << 4) 572 #define DEM_DLY_N (1 << 14) 573 #define DISABLE_DEM (1 << 15) 574 575 576 // R 2D REG_DAC_CTRL2 577 #define DACPR_INVERT (1) 578 #define DAC_PL_INVERT (1 << 1) 579 #define DAC_STEP_SEL_DACCLK (4 << 4) 580 #define DAC_STEP_SEL_DLY1_MCLK (5 << 4) 581 #define DAC_STEP_SEL_DLY2_MCLK (6 << 4) 582 #define DAC_STEP_SEL_DLY3_MCLK (7 << 4) 583 #define DSMOD_DITHER(x) (x << 7) 584 #define DEM_DITHER(x) (x << 12) 585 586 587 // R 2F REG_DAC_DGAIN_CTRL 588 #define DAC0_TO_DAC1_ST(x) (x << 0) 589 #define DAC1_TO_DAC0_ST(x) (x << 8) 590 591 // R 30 REG_ADC_DGAIN_CTRL 592 #define DGAINL_ADC0(x) (x) 593 #define ADC_TO_DAC_ST1(x) (x << 8) 594 #define ADC_TO_DAC_ST0(x) (x << 12) 595 596 // R 31 REG_MUTE_CTRL 597 #define ADC_SMUTE_EN (1 << 1) 598 #define ADC_ZC_UP_EN (1 << 2) 599 #define SMUTE_CTRL (1 << 8) 600 #define SMUTE_EN (1 << 9) 601 #define AMUTE_CTRL (1 << 10) 602 #define AMUTE_EN (1 << 11) 603 #define DAC_ZC_UP_EN (1 << 12) 604 #define PGA_SMUTE_STEP_128 (0 << 14) 605 #define PGA_SMUTE_STEP_32 (1 << 14) 606 #define PGA_SMUTE_STEP_16 (2 << 14) 607 #define PGA_SMUTE_STEP_1 (3 << 14) 608 609 610 // R 32 REG_HSVOL_CTRL 611 #define HSPGA1_VOL(x) (x << 0) 612 #define HSPGA0_VOL(x) (x << 6) 613 #define MUTE_HSPGA1 (1 << 12) 614 #define MUTE_HSPGA0 (1 << 13) 615 #define HSPGA_MUTE_AUTO_MODE (1 << 14) 616 #define HSPGA_MUTE_EN (1 << 15) 617 618 619 // R 33 REG_DACL_CTRL 620 #define DGAINL_DAC(x) (x << 0) 621 #define DAC_CH_SEL0_LEFT (0) 622 #define DAC_CH_SEL0_RIGHT (1 << 9) 623 #define DAC_MIXER_L (1 << 14) 624 #define DAC_MIXER_R (1 << 15) 625 626 627 // R 34 REG_DACR_CTRL 628 #define DGAINR_DAC(x) (x << 0) 629 #define DAC_CH_SEL1_LEFT (0) 630 #define DAC_CH_SEL1_RIGHT (1 << 9) 631 632 // R 38 REG_ADC_DRC_KNEE_IP12 633 #define DRC_KNEE1_IP_ADC1(x) (x << 0) 634 #define DRC_SMTH_ENA_ADC1 (1 << 7) 635 #define DRC_KNEE2_IP_ADC1(x) (x << 8) 636 #define DRC_ENA_ADC1 (1 << 15) 637 638 639 // R 39 REG_ADC_DRC_KNEE_IP34 640 #define DRC_KNEE3_IP_ADC1(x) (x << 0) 641 #define DRC_KNEE4_IP_ADC1(x) (x << 8) 642 643 644 // R 3A REG_ADC_DRC_SLOPES 645 #define DRC_LMT_SLP_ADC1_0 (0) 646 #define DRC_LMT_SLP_ADC1_1_2 (1) 647 #define DRC_LMT_SLP_ADC1_1_4 (2) 648 #define DRC_LMT_SLP_ADC1_1_8 (3) 649 #define DRC_LMT_SLP_ADC1_1_16 (4) 650 #define DRC_LMT_SLP_ADC1_1_32 (5) 651 #define DRC_LMT_SLP_ADC1_1_64 (6) 652 #define DRC_LMT_SLP_ADC1_1 (7) 653 654 #define DRC_CMP1_SLP_ADC1_0 (0) 655 #define DRC_CMP1_SLP_ADC1_1_2 (1 << 3) 656 #define DRC_CMP1_SLP_ADC1_1_4 (2 << 3) 657 #define DRC_CMP1_SLP_ADC1_1_8 (3 << 3) 658 #define DRC_CMP1_SLP_ADC1_1_16 (4 << 3) 659 #define DRC_CMP1_SLP_ADC1_1 (7 << 3) 660 661 #define DRC_CMP2_SLP_ADC1_0 (0) 662 #define DRC_CMP2_SLP_ADC1_1_2 (1 << 6) 663 #define DRC_CMP2_SLP_ADC1_1_4 (2 << 6) 664 #define DRC_CMP2_SLP_ADC1_1_8 (3 << 6) 665 #define DRC_CMP2_SLP_ADC1_1_16 (4 << 6) 666 #define DRC_CMP2_SLP_ADC1_1 (7 << 6) 667 668 #define DRC_EXP_SLP_ADC1_1_1 (0) 669 #define DRC_EXP_SLP_ADC1_2_1 (1 << 9) 670 #define DRC_EXP_SLP_ADC1_4_1 (2 << 9) 671 672 #define DRC_NG_SLP_ADC1_1_1 (0) 673 #define DRC_NG_SLP_ADC1_2_1 (1 << 12) 674 #define DRC_NG_SLP_ADC1_4_1 (2 << 12) 675 #define DRC_NG_SLP_ADC1_8_1 (3 << 12) 676 677 678 679 // R 3B REG_ADC_DRC_ATKDCY 680 #define DRC_DCY_ADC1_63 (0) 681 #define DRC_DCY_ADC1_127 (1) 682 #define DRC_DCY_ADC1_255 (2) 683 #define DRC_DCY_ADC1_511 (3) 684 #define DRC_DCY_ADC1_1023 (4) 685 #define DRC_DCY_ADC1_2047 (5) 686 #define DRC_DCY_ADC1_4095 (6) 687 #define DRC_DCY_ADC1_8191 (7) 688 #define DRC_DCY_ADC1_16383 (8) 689 #define DRC_DCY_ADC1_32757 (9) 690 #define DRC_DCY_ADC1_65535 (10) 691 692 #define DRC_ATK_ADC1_x1 (0) 693 #define DRC_ATK_ADC1_x3 (1 << 4) 694 #define DRC_ATK_ADC1_x7 (2 << 4) 695 #define DRC_ATK_ADC1_x15 (3 << 4) 696 #define DRC_ATK_ADC1_x31 (4 << 4) 697 #define DRC_ATK_ADC1_x63 (5 << 4) 698 #define DRC_ATK_ADC1_x127 (6 << 4) 699 #define DRC_ATK_ADC1_x255 (7 << 4) 700 #define DRC_ATK_ADC1_x511 (8 << 4) 701 #define DRC_ATK_ADC1_x1023 (9 << 4) 702 #define DRC_ATK_ADC1_x2047 (10 << 4) 703 #define DRC_ATK_ADC1_x4095 (11 << 4) 704 #define DRC_ATK_ADC1_x8191 (12 << 4) 705 706 707 #define DRC_PK_COEF2_ADC1_63 (0) 708 #define DRC_PK_COEF2_ADC1_127 (1 << 8) 709 #define DRC_PK_COEF2_ADC1_255 (2 << 8) 710 #define DRC_PK_COEF2_ADC1_511 (3 << 8) 711 #define DRC_PK_COEF2_ADC1_1023 (4 << 8) 712 #define DRC_PK_COEF2_ADC1_2047 (5 << 8) 713 #define DRC_PK_COEF2_ADC1_4095 (6 << 8) 714 #define DRC_PK_COEF2_ADC1_8191 (7 << 8) 715 716 #define DRC_PK_COEF1_ADC1_x1 (0) 717 #define DRC_PK_COEF1_ADC1_x3 (1 << 12) 718 #define DRC_PK_COEF1_ADC1_x7 (2 << 12) 719 #define DRC_PK_COEF1_ADC1_x15 (3 << 12) 720 #define DRC_PK_COEF1_ADC1_x31 (4 << 12) 721 #define DRC_PK_COEF1_ADC1_x63 (5 << 12) 722 #define DRC_PK_COEF1_ADC1_x127 (6 << 12) 723 #define DRC_PK_COEF1_ADC1_x255 (7 << 12) 724 725 726 // R 45 REG_DAC_DRC_KNEE_IP12 727 #define DRC_KNEE1_IP_DAC(x) (x) 728 #define DRC_SMTH_ENA_DAC (1 << 7) 729 #define DRC_KNEE2_IP_DAC(x) (x << 8) 730 #define DRC_ENA_DAC (1 << 15) 731 732 733 // R 46 REG_DAC_DRC_KNEE_IP34 734 #define DRC_KNEE3_IP_DAC(x) (x) 735 #define DRC_KNEE4_IP_DAC(x) (x << 8) 736 737 // R 47 REG_DAC_DRC_SLOPES 738 #define DRC_LMT_SLP_DAC_0 (0) 739 #define DRC_LMT_SLP_DAC_1_2 (1) 740 #define DRC_LMT_SLP_DAC_1_4 (2) 741 #define DRC_LMT_SLP_DAC_1_8 (3) 742 #define DRC_LMT_SLP_DAC_1_16 (4) 743 #define DRC_LMT_SLP_DAC_1_32 (5) 744 #define DRC_LMT_SLP_DAC_1_64 (6) 745 #define DRC_LMT_SLP_DAC_1_1 (7) 746 747 #define DRC_CMP1_SLP_DAC_0 (0) 748 #define DRC_CMP1_SLP_DAC_1_2 (1 << 3) 749 #define DRC_CMP1_SLP_DAC_1_4 (2 << 3) 750 #define DRC_CMP1_SLP_DAC_1_8 (3 << 3) 751 #define DRC_CMP1_SLP_DAC_1_16 (4 << 3) 752 #define DRC_CMP1_SLP_DAC_1 (7 << 3) 753 754 #define DRC_CMP2_SLP_DAC_0 (0) 755 #define DRC_CMP2_SLP_DAC_1_2 (1 << 6) 756 #define DRC_CMP2_SLP_DAC_1_4 (2 << 6) 757 #define DRC_CMP2_SLP_DAC_1_8 (3 << 6) 758 #define DRC_CMP2_SLP_DAC_1_16 (4 << 6) 759 #define DRC_CMP2_SLP_DAC_1 (7 << 6) 760 761 #define DRC_EXP_SLP_DAC_1_1 (0) 762 #define DRC_EXP_SLP_DAC_2_1 (1 << 9) 763 #define DRC_EXP_SLP_DAC_4_1 (2 << 9) 764 #define DRC_EXP_SLP_DAC_8_1 (3 << 9) 765 766 #define DRC_NG_SLP_DAC_1_1 (0) 767 #define DRC_NG_SLP_DAC_2_1 (1 << 12) 768 #define DRC_NG_SLP_DAC_4_1 (2 << 12) 769 #define DRC_NG_SLP_DAC_8_1 (3 << 12) 770 771 772 // R 48 REG_DAC_DRC_ATKDCY 773 #define DRC_DCY_DAC_63 (0) 774 #define DRC_DCY_DAC_127 (1) 775 #define DRC_DCY_DAC_255 (2) 776 #define DRC_DCY_DAC_511 (3) 777 #define DRC_DCY_DAC_1023 (4) 778 #define DRC_DCY_DAC_2047 (5) 779 #define DRC_DCY_DAC_4095 (6) 780 #define DRC_DCY_DAC_8191 (7) 781 #define DRC_DCY_DAC_16383 (8) 782 #define DRC_DCY_DAC_32757 (9) 783 #define DRC_DCY_DAC_65535 (10) 784 785 #define DRC_ATK_DAC_x1 (0) 786 #define DRC_ATK_DAC_x3 (1 << 4) 787 #define DRC_ATK_DAC_x7 (2 << 4) 788 #define DRC_ATK_DAC_x15 (3 << 4) 789 #define DRC_ATK_DAC_x31 (4 << 4) 790 #define DRC_ATK_DAC_x63 (5 << 4) 791 #define DRC_ATK_DAC_x127 (6 << 4) 792 #define DRC_ATK_DAC_x255 (7 << 4) 793 #define DRC_ATK_DAC_x511 (8 << 4) 794 #define DRC_ATK_DAC_x1023 (9 << 4) 795 #define DRC_ATK_DAC_x2047 (10 << 4) 796 #define DRC_ATK_DAC_x4095 (11 << 4) 797 #define DRC_ATK_DAC_x8191 (12 << 4) 798 799 800 #define DRC_PK_COEF2_DAC_63 (0) 801 #define DRC_PK_COEF2_DAC_127 (1 << 8) 802 #define DRC_PK_COEF2_DAC_255 (2 << 8) 803 #define DRC_PK_COEF2_DAC_511 (3 << 8) 804 #define DRC_PK_COEF2_DAC_1023 (4 << 8) 805 #define DRC_PK_COEF2_DAC_2047 (5 << 8) 806 #define DRC_PK_COEF2_DAC_4095 (6 << 8) 807 #define DRC_PK_COEF2_DAC_8191 (7 << 8) 808 809 #define DRC_PK_COEF1_DAC_x1 (0) 810 #define DRC_PK_COEF1_DAC_x3 (1 << 12) 811 #define DRC_PK_COEF1_DAC_x7 (2 << 12) 812 #define DRC_PK_COEF1_DAC_x15 (3 << 12) 813 #define DRC_PK_COEF1_DAC_x31 (4 << 12) 814 #define DRC_PK_COEF1_DAC_x63 (5 << 12) 815 #define DRC_PK_COEF1_DAC_x127 (6 << 12) 816 #define DRC_PK_COEF1_DAC_x255 (7 << 12) 817 818 819 // R 4C REG_MODE_CTRL 820 #define DACIN_SRC_DAC_BIQUAD (0) 821 #define DACIN_SRC_DRC_DAC (1) 822 #define DACIN_SRC_DAC_MIXER (2) 823 #define DACIN_SRC_BUILDIN_SINE (3) 824 #define DACIN_SRC_DRC_LAW_DECODE (4) 825 826 827 // R 50 REG_CLASSG_CTRL 828 #define CLASSG_EN (1) 829 #define CLASSG_CMP_EN_L_DAC (1 << 1) 830 #define CLASSG_CMP_EN_R_DAC (1 << 2) 831 #define CLASSG_THRSLD_1_16 (0) 832 #define CLASSG_THRSLD_1_8 (1 << 4) 833 #define CLASSG_THRSLD_3_16 (2 << 4) 834 #define CLASSG_THRSLD_1_4 (3 << 4) 835 836 #define CLASSG_TIMER_1MS (1 << 8) 837 #define CLASSG_TIMER_2MS (2 << 8) 838 #define CLASSG_TIMER_8MS (4 << 8) 839 #define CLASSG_TIMER_16MS (8 << 8) 840 #define CLASSG_TIMER_32MS (16 << 8) 841 #define CLASSG_TIMER_64MS (32 << 8) 842 #define CLASSG_CLK_SRC_2M (0) 843 #define CLASSG_CLK_SRC_1_3MCLK (1 << 14) 844 #define CLASSG_CLK_SRC_MCLK (2 << 14) 845 #define CLASSG_CLK_SRC_DISABLE_CLK (3 << 14) 846 847 // R 51 REG_OPT_EFU 848 #define WL_BIN_POS (0) 849 #define WL_BIN_MSK (0x3F << WL_BIN_POS) 850 851 #define STROBE_IN (1 << 6) 852 #define PGEN_IN (1 << 7) 853 #define NR_IN (1 << 8) 854 #define STANDBY_IN (1 << 15) 855 856 // R 55 REG_MISC_CTRL 857 #define D2A_LOOP (1 << 1) 858 #define RAM_TEST_START (1 << 3) 859 #define SPIEN (1 << 15) 860 #define I2CEN (0) 861 862 // R 58 REG_I2C_DEVICE_ID 863 #define Software_ID (0x3) 864 #define Silicon_Revision_ID (0x7 << 2) 865 #define JKDETL (0x1 << 5) 866 #define GPIO3JD2 (0x1 << 6) 867 #define GPIO2JD1 (0x1 << 7) 868 #define I2C_DEVICE_ID (0x3F << 9) 869 870 // R 59 REG_SARDOUT_RAM_STATUS 871 #define SARADC_DOUT (0xff) 872 #define ANALOG_MUTE (0x1 << 10) 873 #define RAM_TEST_FAIL (0x3 << 11) 874 #define RATM_TEST_FINISH (0x1 << 13) 875 876 877 // R 66 REG_BIAS_ADJ 878 #define BIASADJ_NORMAL (0x0) 879 #define BIASADJ_9 (0x1 << 0) 880 #define BIASADJ_17 (0x2 << 0) 881 #define BIASADJ_11 (0x3 << 0) 882 #define VMIDSEL_OPEN (0x0 << 4) 883 #define VMIDSEL_25K_OHM (0x1 << 4) 884 #define VMIDSEL_125K_OHM (0x2 << 4) 885 #define VMIDSEL_2P5K_OHM (0x3 << 4) 886 #define VMIDEN (0x1 << 6) 887 #define MUTEL (0x1 << 13) 888 889 // R 68 REG_TRIM_SETTINGS 890 #define DIS_OC_RIGHT (0x2) 891 #define DIS_OC_LEFT (0x4) 892 #define INTEG_ICUTHS (0x1 << 8) 893 #define INTEG_IBCTRHS (0x1 << 9) 894 #define DRV_ICUTHS (0x1 << 14) 895 #define DRV_IBCTRHS (0x1 << 15) 896 897 898 // R 69 REG_ANALOG_CONTROL_1 899 #define ENJKDETL (0x1 << 0) 900 #define JKDETLPOL (0x1 << 1) 901 #define JD1POL (0x1 << 2) 902 #define GPIO2THH_P85x (0x0) 903 #define GPIO2THH_P78x (0x2 << 4) 904 #define GPIO2THH_P6x (0x3 << 4) 905 #define GPIO2THL_P22x (0x0) 906 #define GPIO2THL_P4x (0x2 << 6) 907 #define GPIO2THL_P5x (0x3 << 6) 908 #define Pullup_GPIO2_1M (0x0) 909 #define Pullup_GPIO2_100K (0x1 << 8) 910 #define GPIO3THH_P85x (0x0) 911 #define GPIO3THH_P78x (0x2 << 9) 912 #define GPIO3THH_P6x (0x3 << 9) 913 #define GPIO3THL_P22x (0x0) 914 #define GPIO3THL_P4x (0x2 << 11) 915 #define GPIO3THL_P5x (0x3 << 11) 916 #define Pullup_GPIO3_1M (0x0) 917 #define Pullup_GPIO3_100K (0x1 << 13) 918 919 920 921 // R 6A REG_ANALOG_CONTROL_2 922 #define CAP_0 (0x1) 923 #define CAP_1 (0x1 << 1) 924 #define MUTEMICN (0x1 << 2) 925 #define MUTEMICP (0x1 << 3) 926 #define AB_ADJ (0x1 << 7) 927 928 929 930 // R 71 REG_ANALOG_ADC_1 931 #define CHOPF0_DIV2 (0) 932 #define CHOPF0_DIV4 (0x1 << 0) 933 #define CHOPF0_DIV8 (0x2 << 0) 934 #define CHOPF0_DIV16 (0x3 << 0) 935 #define CHOPORDER (0x1 << 2) 936 #define CHOPFIXED (0x1 << 3) 937 #define CHOPRESETN (0x1 << 4) 938 #define CHOPPHASE (0x1 << 5) 939 #define CHOPENABLE (0x1 << 6) 940 #define RESETL (0x1 << 8) 941 942 943 // R 72 REG_ANALOG_ADC_2 944 #define MON4TH (0x1 << 0) 945 #define MON3RD (0x1 << 1) 946 #define MON2ND (0x1 << 2) 947 #define MON1ST (0x1 << 3) 948 #define MONADD (0x1 << 4) 949 #define LFSRRESETN (0x1 << 5) 950 #define PDNOTL (0x1 << 6) 951 952 #define VREFSEL_ANALOG (0x0 << 8) 953 #define VREFSEL_VMIDE (0x1 << 8) 954 #define VREFSEL_VMIDE_P5DB (0x2 << 8) 955 #define VREFSEL_ANALOG_1DB (0x3 << 8) 956 957 #define BIAS_NORMAL (0x0 << 10) 958 #define BIAS_BOUBLE (0x1 << 10) 959 #define BIAS_HALF (0x2 << 10) 960 #define BIAS_QUARTER (0x3 << 10) 961 #define ADC_UPL (0x1 << 13) 962 963 964 965 // R 73 REG_RDAC 966 #define DACVREFSEL(x) (x << 2) 967 #define CLK_DAC_DELAY_0NSEC (0) 968 #define CLK_DAC_DELAY_1NSEC (0x1 << 4) 969 #define CLK_DAC_DELAY_2NSEC (0x2 << 4) 970 #define CLK_DAC_DELAY_3NSEC (0x3 << 4) 971 #define CLK_DAC_DELAY_4NSEC (0x4 << 4) 972 #define CLK_DAC_DELAY_N3NSEC (0x5 << 4) 973 #define CLK_DAC_DELAY_N2NSEC (0x6 << 4) 974 #define CLK_DAC_DELAY_N1NSEC (0x7 << 4) 975 976 #define FC_CTR (0x1 << 7) 977 #define CLK_DAC_EN_R (0x1 << 9) 978 #define CLK_DAC_EN_L (0x1 << 8) 979 #define DAC_EN_R (0x1 << 13) 980 #define DAC_EN_L (0x1 << 12) 981 #define FS_BCLK_ENB (0x1 << 15) 982 983 984 // R 74 REG_MIC_BIAS 985 #define MICBIASLVL1_VDDA (0) 986 #define MICBIASLVL1_1x (0x1 << 0) 987 #define MICBIASLVL1_1P1x (0x2 << 0) 988 #define MICBIASLVL1_1P2x (0x3 << 0) 989 #define MICBIASLVL1_1P3x (0x4 << 0) 990 #define MICBIASLVL1_1P4x (0x5 << 0) 991 #define MICBIASLVL1_1P53x (0x6 << 0) 992 993 #define NOCAP (0x1 << 6) 994 #define POWERUP (0x1 << 8) 995 #define LOWNOISE (0x1 << 10) 996 #define INT2KA (0x1 << 12) 997 #define INT2KB (0x1 << 14) 998 999 1000 // R 76 REG_BOOST 1001 #define NAMP_THRSHLD(x) (x << 0) 1002 #define PAMP_THRSHLD(x) (x << 2) 1003 #define HS_SHRT_THRESHLD(x) (x << 4) 1004 #define EN_SHRT_SHTDWN (0x1 << 6) 1005 #define SHRT_SHTDWN_DIG_EN (0x1 << 7) 1006 #define BOOSTGDIS (0x1 << 8) 1007 #define BOOSTDIS (0x1 << 9) 1008 #define BYPS_IBCTR (0x1 << 10) 1009 #define DISCHRG (0x1 << 11) 1010 #define BIASEN (0x1 << 12) 1011 #define PDVMDFST (0x1 << 13) 1012 #define STG2_SEL (0x1 << 14) 1013 #define CLR_APR_EMRGENCY_SHTDWN (0x1 << 15) 1014 1015 1016 // R 77 REG_FEPGA 1017 #define FEPGA_MODEL_ANIT_ALIASING (0x1 << 0) 1018 #define FEPGA_MODEL_DISCONNECT_MICPN (0x1 << 1) 1019 #define FEPGA_MODEL_12KOHM_SHORT (0x1 << 3) 1020 1021 #define IBCTR_CODE(x) (x << 8) 1022 #define IB_LOOP_CTR (0x1 << 11) 1023 #define CMLCK_ADJ(x) (x << 12) 1024 #define ACDC_CTRL_MICP_VREF (0x1 << 14) 1025 #define ACDC_CTRL_MICN_VREF (0x1 << 15) 1026 1027 1028 // R 7F REG_POWER_UP_CONTROL 1029 #define PUP_MAIN_DRV_LEFT_HP (0x1 << 0) 1030 #define PUP_MAIN_DRV_RIGHT_HP (0x1 << 1) 1031 #define PUP_DRV_INSTG_LEFT_HP (0x1 << 2) 1032 #define PUP_DRV_INSTG_RIGHT_HP (0x1 << 3) 1033 #define PUP_INTEG_LEFT_HP (0x1 << 4) 1034 #define PUP_INTEG_RIGHT_HP (0x1 << 5) 1035 #define FEPGA_GAIN(x) (x << 8) 1036 #define PUFEPGA (0x1 << 14) 1037 1038 1039 1040 // R 80 REG_CHARGE_PUMP_AND_POWER_DOWN_CONTROL 1041 #define SHCIRSEL1_HIGH (0x1) 1042 #define SHCIRSEL1_LOW (0) 1043 #define SHCIRSEL2_HIGH (0x1 << 1) 1044 #define SHCIRSEL2_LOW (0) 1045 #define DISCHARGEVPOS (0x1 << 2) 1046 #define DISCHARGEVEE (0x1 << 3) 1047 #define PRECHARGE (0x1 << 4) 1048 #define RNIN (0x1 << 5) 1049 #define JAMFORCE1 (0x1 << 6) 1050 #define JAMFORCE2 (0x1 << 7) 1051 #define PD_DAC_ENABLE (0x3 << 8) 1052 #define JAMNODCLOW (0x1 << 10) 1053 #define ADCDAT_DS (0x1 << 12) 1054 #define FS_DS (0x1 << 13) 1055 #define BCLK_DS (0x1 << 14) 1056 1057 1058 // R 81 REG_CHARGE_PUMP_INPUT_READ 1059 #define FORCE1BUF (0x1 << 0) 1060 #define VCOMPBUF (0x1 << 1) 1061 #define VPOSOK (0x1 << 2) 1062 #define RN2BUF (0x1 << 3) 1063 #define NODCBUF (0x1 << 4) 1064 #define MODE1BUF (0x1 << 5) 1065 #define APR_EMRGNCY_SHTDWN (0x1 << 15) 1066 1067 1068 // R 82 REG_GENERAL_STATUS 1069 #define GPIO1_IN (0x1 << 0) 1070 #define GPIO2_IN (0x1 << 1) 1071 #define GPIO3_IN (0x1 << 2) 1072 #define GPIO4_IN (0x1 << 3) 1073 #define JKDETL1 (0x1 << 4) 1074 #define JKDET_ON (0x1 << 5) 1075 #define JK_INSERT_INTR (0x1 << 6) 1076 #define JK_EJECT_INTR (0x1 << 7) 1077 #define OUT1 (0x1 << 8) 1078 #define OUT2 (0x1 << 9) 1079 #define OUT1_OUT (0x1 << 10) 1080 #define OUT2_OUT (0x1 << 11) 1081 1082 typedef struct 1083 { 1084 char *i2c_bus_name; 1085 1086 char *i2s_bus_name; 1087 1088 rt_int32_t pin_phonejack_en; 1089 1090 rt_int32_t pin_phonejack_det; 1091 1092 } S_NU_NAU88L25_CONFIG; 1093 1094 int nu_hw_nau88l25_init(S_NU_NAU88L25_CONFIG *psCodecConfig); 1095 1096 #endif /* __ACODEC_NAU88L25_H__ */ 1097