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Searched refs:L0 (Results 1 – 11 of 11) sorted by relevance

/bsp/fujitsu/mb9x/mb9bf506r/drivers/
A Dfm3_uart.c418 uart->uart_regs->ESCR_f.L0 = 1; in uart03_configure()
423 uart->uart_regs->ESCR_f.L0 = 0; in uart03_configure()
428 uart->uart_regs->ESCR_f.L0 = 1; in uart03_configure()
433 uart->uart_regs->ESCR_f.L0 = 0; in uart03_configure()
438 uart->uart_regs->ESCR_f.L0 = 0; in uart03_configure()
598 uart->uart_regs->ESCR_f.L0 = 1; in uart47_configure()
603 uart->uart_regs->ESCR_f.L0 = 0; in uart47_configure()
608 uart->uart_regs->ESCR_f.L0 = 1; in uart47_configure()
613 uart->uart_regs->ESCR_f.L0 = 0; in uart47_configure()
618 uart->uart_regs->ESCR_f.L0 = 0; in uart47_configure()
/bsp/xuantie/xiaohui/c907/
A DREADME.md21 • 混合分支预测机制，改进版的 G-Shared 分支预测器和 L0 BTB、 RAS；
/bsp/xuantie/xiaohui/c908/
A DREADME.md21 • 混合分支预测机制，改进版的 G-Shared 分支预测器和 L0 BTB、 RAS；
/bsp/bf533/vdsp/
A Dbf533_basiccrt.s101 L0 = R7; define
/bsp/CME_M7/StdPeriph_Driver/src/
A Dcmem7_ddr.c334 DDRC->RDQ_b.L3 = DDRC->RDQ_b.L2 = DDRC->RDQ_b.L1 = DDRC->RDQ_b.L0 = 0x32; in DDR2_conf()
/bsp/stm32/
A DREADME.md75 | **L0 系列** | …
/bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/
A Dmb9bf506r.h3590 __IO uint8_t L0 : 1; member
3666 __IO uint8_t L0 : 1; member
3852 __IO uint8_t L0 : 1; member
4015 __IO uint8_t L0 : 1; member
/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/
A Dmb9b610s.h4608 __IO uint8_t L0 : 1; member
4684 __IO uint8_t L0 : 1; member
4870 __IO uint8_t L0 : 1; member
5033 __IO uint8_t L0 : 1; member
A Dmb9b610t.h4828 __IO uint8_t L0 : 1; member
4902 __IO uint8_t L0 : 1; member
5081 __IO uint8_t L0 : 1; member
5242 __IO uint8_t L0 : 1; member
/bsp/CME_M7/StdPeriph_Driver/inc/
A Dcmem7.h7719 …__IO uint32_t L0 : 7; /*!< FPGA version, read dq delay of byte lane0 … member
/bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/
A Dmb9b560r.h5426 __IO uint8_t L0 : 1; /* for UART/CSIO */ member

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