| /bsp/fujitsu/mb9x/mb9bf506r/drivers/ |
| A D | fm3_uart.c | 419 uart->uart_regs->ESCR_f.L1 = 0; in uart03_configure()
424 uart->uart_regs->ESCR_f.L1 = 1; in uart03_configure()
429 uart->uart_regs->ESCR_f.L1 = 1; in uart03_configure()
434 uart->uart_regs->ESCR_f.L1 = 0; in uart03_configure()
439 uart->uart_regs->ESCR_f.L1 = 0; in uart03_configure()
599 uart->uart_regs->ESCR_f.L1 = 0; in uart47_configure()
604 uart->uart_regs->ESCR_f.L1 = 1; in uart47_configure()
609 uart->uart_regs->ESCR_f.L1 = 1; in uart47_configure()
614 uart->uart_regs->ESCR_f.L1 = 0; in uart47_configure()
619 uart->uart_regs->ESCR_f.L1 = 0; in uart47_configure()
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| /bsp/mm32f526x/ |
| A D | README.md | 26 - 4KB L1 指令缓存（I-Cache）和 4KB L1 数据缓存（D-Cache）
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| /bsp/phytium/aarch32/ |
| A D | Kconfig | 31 prompt "Use Aarch64 L1 to Aarch32 code"
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| /bsp/xuantie/xiaohui/c907/ |
| A D | README.md | 27 • 支持 L1、 L2 两级 TLB， Sv39/Sv48 可配置，支持 Sv32；
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| /bsp/xuantie/xiaohui/c908/ |
| A D | README.md | 27 • 支持 L1、 L2 两级 TLB， Sv39/Sv48 可配置，支持 Sv32；
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| /bsp/bf533/vdsp/ |
| A D | bf533_basiccrt.s | 102 L1 = R7; define
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| A D | bf533_ram.ldf | 37 ** system_heap: L1
39 ** system_stack: L1
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| A D | bf533_sdram_64M.ldf | 41 ** system_heap: L1
43 ** system_stack: L1
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| /bsp/sparkfun-redv/ |
| A D | README.md | 23 - 16KB L1 指令缓存
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| /bsp/microchip/same70/ |
| A D | README_zh.md | 15 …- 32-bit Arm® Cortex®-M7 core + 双精度FPU + L1 cache: 16 Kbytes 数据DCache and 16 Kbytes 指令 Icache; 主频高…
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| A D | README.md | 15 …- 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kby…
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| /bsp/CME_M7/StdPeriph_Driver/src/ |
| A D | cmem7_ddr.c | 334 DDRC->RDQ_b.L3 = DDRC->RDQ_b.L2 = DDRC->RDQ_b.L1 = DDRC->RDQ_b.L0 = 0x32; in DDR2_conf()
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| /bsp/nxp/imx/imx6sx/cortex-a9/cpu/ |
| A D | cortexA9_gcc.S | 305 @ - Invalidate L1 caches
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| /bsp/stm32/stm32h743-st-nucleo/ |
| A D | README.md | 14 …- 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kby…
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| /bsp/stm32/stm32h723-st-nucleo/ |
| A D | README.md | 17 …- 32-bit Arm® Cortex®-M7 CPU with DP-FPU, L1 cache: 32-Kbyte data cache and 32-Kbyte instruction c…
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| /bsp/stm32/stm32f767-st-nucleo/ |
| A D | README.md | 19 - Core: Arm® 32-bit Cortex®-M7 CPU with DPFPU, ART Accelerator™ and L1-cache: 16 Kbytes I/D cache, …
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| /bsp/renesas/rzn2l_etherkit/ |
| A D | rzn_cfg.txt | 817 VSS L1 SYSTEM_VSS - - - - - - - - I "Read only" -
1043 VSS L1 SYSTEM_VSS - - - - - - - - I "Read only" -
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| /bsp/renesas/rzn2l_rsk/ |
| A D | rzn_cfg.txt | 817 VSS L1 SYSTEM_VSS - - - - - - - - I "Read only" -
1043 VSS L1 SYSTEM_VSS - - - - - - - - I "Read only" -
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| /bsp/fujitsu/mb9x/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/ |
| A D | mb9bf506r.h | 3591 __IO uint8_t L1 : 1; member
3667 __IO uint8_t L1 : 1; member
3853 __IO uint8_t L1 : 1; member
4016 __IO uint8_t L1 : 1; member
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| /bsp/fujitsu/mb9x/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/ |
| A D | mb9b610s.h | 4609 __IO uint8_t L1 : 1; member
4685 __IO uint8_t L1 : 1; member
4871 __IO uint8_t L1 : 1; member
5034 __IO uint8_t L1 : 1; member
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| A D | mb9b610t.h | 4829 __IO uint8_t L1 : 1; member
4903 __IO uint8_t L1 : 1; member
5082 __IO uint8_t L1 : 1; member
5243 __IO uint8_t L1 : 1; member
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| /bsp/CME_M7/StdPeriph_Driver/inc/ |
| A D | cmem7.h | 7717 …__IO uint32_t L1 : 6; /*!< FPGA version, read dq delay of byte lane3 … member
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| /bsp/fujitsu/mb9x/mb9bf568r/CMSIS/DeviceSupport/ |
| A D | mb9b560r.h | 5427 __IO uint8_t L1 : 1; /* for UART/CSIO */ member
|