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Searched refs:L1C_CACHEABLE (Results 1 – 4 of 4) sorted by relevance

/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/
A Dbl702_l1c.c107 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Cache_Enable_Set()
182 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Cache_Enable_Set()
184 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Cache_Enable_Set()
306 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Cache_Read_Disable()
327 cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE); in L1C_Set_Wrap()
330 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Set_Wrap()
345 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Set_Wrap()
368 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Set_Way_Disable()
376 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Set_Way_Disable()
378 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Set_Way_Disable()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/
A Dbl602_l1c.c106 cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE); in L1C_Set_Wrap()
109 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Set_Wrap()
124 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Set_Wrap()
148 cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE); in L1C_Set_Way_Disable()
151 tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Set_Way_Disable()
160 tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); in L1C_Set_Way_Disable()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/
A Dl1c_reg.h43 #define L1C_CACHEABLE L1C_CACHEABLE macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/
A Dl1c_reg.h43 #define L1C_CACHEABLE L1C_CACHEABLE macro

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