Searched refs:L2 (Results 1 – 15 of 15) sorted by relevance
72 } > L279 } > L2116 } > L2121 } > L2139 } > L2143 } > L2150 } > L2159 } > L2166 } > L2170 } > L2[all …]
420 uart->uart_regs->ESCR_f.L2 = 0; in uart03_configure()425 uart->uart_regs->ESCR_f.L2 = 0; in uart03_configure()430 uart->uart_regs->ESCR_f.L2 = 0; in uart03_configure()435 uart->uart_regs->ESCR_f.L2 = 0; in uart03_configure()440 uart->uart_regs->ESCR_f.L2 = 1; in uart03_configure()600 uart->uart_regs->ESCR_f.L2 = 0; in uart47_configure()605 uart->uart_regs->ESCR_f.L2 = 0; in uart47_configure()610 uart->uart_regs->ESCR_f.L2 = 0; in uart47_configure()615 uart->uart_regs->ESCR_f.L2 = 0; in uart47_configure()620 uart->uart_regs->ESCR_f.L2 = 1; in uart47_configure()
27 • 支持 L1、 L2 两级 TLB， Sv39/Sv48 可配置，支持 Sv32；
17 个处理器核簇（Cluster），并共享 L2 Cache。主要技术特征如下：
103 L2 = R7; define
16 |cache| 核内集成64KB L1I和64KB L1D Cache以及512KB L2 Cache |
334 DDRC->RDQ_b.L3 = DDRC->RDQ_b.L2 = DDRC->RDQ_b.L1 = DDRC->RDQ_b.L0 = 0x32; in DDR2_conf()
665 …P06_0 L2 - ETH1_TXD3 - - Disabled - - "CANFD1: CANRX1; CMTW1: CMTW1_TOC0; ETHER_ETH1: ETH1_TXD3; G…891 …P06_0 L2 - ETH1_TXD3 - - Disabled - - "CANFD1: CANRX1; CMTW1: CMTW1_TOC0; ETHER_ETH1: ETH1_TXD3; G…
3592 __IO uint8_t L2 : 1; member3668 __IO uint8_t L2 : 1; member3854 __IO uint8_t L2 : 1; member4017 __IO uint8_t L2 : 1; member
4610 __IO uint8_t L2 : 1; member4686 __IO uint8_t L2 : 1; member4872 __IO uint8_t L2 : 1; member5035 __IO uint8_t L2 : 1; member
4830 __IO uint8_t L2 : 1; member4904 __IO uint8_t L2 : 1; member5083 __IO uint8_t L2 : 1; member5244 __IO uint8_t L2 : 1; member
7715 …__IO uint32_t L2 : 6; /*!< FPGA version, read dq delay of byte lane2 … member
5428 __IO uint8_t L2 : 1; /* for UART/CSIO */ member
Completed in 6391 milliseconds