Searched refs:L3 (Results 1 – 6 of 6) sorted by relevance
104 L3 = R7; define
334 DDRC->RDQ_b.L3 = DDRC->RDQ_b.L2 = DDRC->RDQ_b.L1 = DDRC->RDQ_b.L0 = 0x32; in DDR2_conf()
666 …P06_1 L3 - ETH1_REFCLK - - Disabled - - "CANFD1: CANTX1; ETHER_ETH1: ETH1_REFCLK; ETHER_ETH1: ETH1…892 …P06_1 L3 - ETH1_REFCLK - - Disabled - - "CANFD1: CANTX1; ETHER_ETH1: ETH1_REFCLK; ETHER_ETH1: ETH1…
7713 …__IO uint32_t L3 : 6; /*!< FPGA version, read dq delay of byte lane3 … member
5431 __IO uint8_t L3 : 1; /* for CSIO */ member
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