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/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/
A Dhpm_lobs_drv.h162 lobs->LAR = LOBS_UNLOCK_KEY; in lobs_unlock()
172 lobs->LAR = 0; in lobs_lock()
/bsp/efm32/EFM32_Gxxx_DK/
A Dtrace.c85 ITM->LAR = 0xC5ACCE55; in TRACE_SWOSetup()
/bsp/efm32/EFM32GG_DK3750/
A Dtrace.c120 ITM->LAR = 0xC5ACCE55; in TRACE_SWOSetup()
/bsp/efm32/
A Dboard.c239 ITM->LAR = 0xC5ACCE55; in Swo_Configuration()
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/
A Dhpm_lobs_regs.h56 __RW uint32_t LAR; /* 0xFB0: Lock Access Register */ member
/bsp/synwit/libraries/SWM320_CSL/CMSIS/CoreSupport/
A Dcore_cm7.h900 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register … member
1008 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register … member
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/samd21/sam_d2x_asflib/CMSIS/Include/
A Dcore_cm7.h900 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register … member
1008 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register … member
/bsp/rockchip/common/rk_hal/lib/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/mm32l3xx/Libraries/CMSIS/IAR_CORE/
A Dcore_cm7.h900 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register … member
1008 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register … member
/bsp/synwit/libraries/SWM341_CSL/CMSIS/CoreSupport/
A Dcore_cm7.h1052 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1150 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/mm32l07x/Libraries/CMSIS/IAR_CORE/
A Dcore_cm7.h900 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register … member
1008 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register … member
/bsp/tae32f5300/Libraries/CMSIS/Include/
A Dcore_cm7.h1052 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1150 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/renesas/ra6m4-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/renesas/ra8m1-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/renesas/ra8d1-vision-board/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/renesas/ra6m4-iot/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/renesas/ebf_qi_min_6m5/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/renesas/ra4m2-eco/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/renesas/ra2l1-cpk/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/renesas/ra6m3-hmi-board/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/renesas/ra6m3-ek/ra/arm/CMSIS_5/CMSIS/Core/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/
A Dcore_cm7.h886 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register … member
993 …__O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register … member
/bsp/at32/libraries/CMSIS/include/
A Dcore_cm7.h1068 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1166 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
/bsp/airm2m/air32f103/libraries/CMSIS/Include/
A Dcore_cm7.h1056 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1154 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member

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