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/bsp/synwit/libraries/SWM320_drivers/
A Ddrv_gpio.c76 __SWM_PIN(34, M, 0),
77 __SWM_PIN(35, M, 1),
78 __SWM_PIN(36, M, 2),
79 __SWM_PIN(37, M, 3),
80 __SWM_PIN(38, M, 4),
81 __SWM_PIN(39, M, 5),
82 __SWM_PIN(40, M, 6),
83 __SWM_PIN(41, M, 7),
84 __SWM_PIN(42, M, 8),
85 __SWM_PIN(43, M, 9),
[all …]
/bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/
A Dhal_fll.c64 unsigned int M = (freq << D) / fref; in __rt_fll_get_mult_div_from_freq() local
72 while (M >= 10000) { in __rt_fll_get_mult_div_from_freq()
73 M >>= 1; in __rt_fll_get_mult_div_from_freq()
77 if (D == 0) fres = fref*M; in __rt_fll_get_mult_div_from_freq()
78 else fres = (fref*M + (1<<(D-1)))>>D; /* Rounding */ in __rt_fll_get_mult_div_from_freq()
81 fres = (fref * M + (1 << (D - 1))) >> D; /* Rounding */ in __rt_fll_get_mult_div_from_freq()
84 *mult = M; in __rt_fll_get_mult_div_from_freq()
A Dhal_fll_pi.c69 unsigned int M = (freq << D) / fref; in fll_get_mult_div_from_frequency() local
72 fres = (fref * M + (1 << (D - 1))) >> D; /* Rounding */ in fll_get_mult_div_from_frequency()
74 *mult = M; in fll_get_mult_div_from_frequency()
/bsp/nxp/imx/imxrt/imxrt1052-seeed-ArchMix/
A DREADME.md7 …/www.seeedstudio.com/) 推出的一款基于 i.MX RT 1050 系列芯片的开发板，板载一颗 RGB 灯和一个用户按键，外扩 32M SDRAM，板载资源丰富，运行速度快（主…
17 | 外部存储器 | 32M SDRAM、8M QSPI FLASH（存储代码） |
71 | SDRAM | 支持 | 32M SDRAM，后面 2M 作为 Non Cache 区域 |
/bsp/synwit/libraries/SWM341_drivers/
A Ddrv_gpio.c120 __SWM_PIN(80, M, 0),
121 __SWM_PIN(81, M, 1),
122 __SWM_PIN(82, M, 2),
123 __SWM_PIN(83, M, 3),
124 __SWM_PIN(84, M, 4),
125 __SWM_PIN(85, M, 5),
126 __SWM_PIN(86, M, 6),
127 __SWM_PIN(87, M, 7),
128 __SWM_PIN(88, M, 8),
129 __SWM_PIN(89, M, 9),
[all …]
/bsp/n32/libraries/N32WB452_Firmware_Library/n32wb452_ble_driver/inc/
A Dsmpc.h139 uint8_t* M; // pointer to memory allocated by calling function member
154 uint8_t M[65]; member
160 uint8_t M[53]; member
170 uint8_t M[65]; member
176 uint8_t M[80]; member
/bsp/xuantie/virt64/c906/
A DREADME_cn.md193 Domain0 Region00 : 0x0000000000100000-0x0000000000100fff M: (I,R,W) S/U: (R,W)
194 Domain0 Region01 : 0x0000000010000000-0x0000000010000fff M: (I,R,W) S/U: (R,W)
195 Domain0 Region02 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: ()
196 Domain0 Region03 : 0x0000000080040000-0x000000008005ffff M: (R,W) S/U: ()
197 Domain0 Region04 : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: ()
198 Domain0 Region05 : 0x000000000c400000-0x000000000c5fffff M: (I,R,W) S/U: (R,W)
200 Domain0 Region07 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
294 Domain0 Region02 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: ()
295 Domain0 Region03 : 0x0000000080040000-0x000000008005ffff M: (R,W) S/U: ()
296 Domain0 Region04 : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: ()
[all …]
A DREADME.md191 Domain0 Region00 : 0x0000000000100000-0x0000000000100fff M: (I,R,W) S/U: (R,W)
192 Domain0 Region01 : 0x0000000010000000-0x0000000010000fff M: (I,R,W) S/U: (R,W)
193 Domain0 Region02 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: ()
194 Domain0 Region03 : 0x0000000080040000-0x000000008005ffff M: (R,W) S/U: ()
195 Domain0 Region04 : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: ()
196 Domain0 Region05 : 0x000000000c400000-0x000000000c5fffff M: (I,R,W) S/U: (R,W)
198 Domain0 Region07 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X)
292 Domain0 Region02 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: ()
293 Domain0 Region03 : 0x0000000080040000-0x000000008005ffff M: (R,W) S/U: ()
294 Domain0 Region04 : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: ()
[all …]
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/CMSIS/
A DREADME.md20 |[Core(M)](http://arm-software.github.io/CMSIS_5/Core/html/index.html) | All Cortex-M, SecurCore |…
24 …l Cortex-M | Collection of efficient neural network kernels developed to maximize the performance …
26 …ub.io/CMSIS_5/RTOS2/html/index.html)| All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with A…
31 |[Zone](http://arm-software.github.io/CMSIS_5/Zone/html/index.html) | All Cortex-M | Defines met…
37 - Support for Armv8.1M Architecture and Cortex-M55 (release in March 2020)
38 …- CMSIS-DSP is fully ported to SIMD for Cortex-M family (Armv8.1-M) and Cortex-A & Cortex-R with …
60 …ted Firmware provides a reference implementation of secure world software for Armv8-A and Armv8-M.|
67 | CMSIS/Core | CMSIS-Core(M) related files (for release) |
69 | CMSIS/CoreValidation | Validation for Core(M) and Core(A) (NOT part of release) |
74 | CMSIS/RTOS | RTOS v1 related files (for Cortex-M) |
[all …]
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/CMSIS/
A DREADME.md20 |[Core(M)](http://arm-software.github.io/CMSIS_5/Core/html/index.html) | All Cortex-M, SecurCore |…
24 …l Cortex-M | Collection of efficient neural network kernels developed to maximize the performance …
26 …ub.io/CMSIS_5/RTOS2/html/index.html)| All Cortex-M, Cortex-A5/A7/A9 | Extends CMSIS-RTOS v1 with A…
31 |[Zone](http://arm-software.github.io/CMSIS_5/Zone/html/index.html) | All Cortex-M | Defines met…
37 - Support for Armv8.1M Architecture and Cortex-M55 (release in March 2020)
38 …- CMSIS-DSP is fully ported to SIMD for Cortex-M family (Armv8.1-M) and Cortex-A & Cortex-R with …
60 …ted Firmware provides a reference implementation of secure world software for Armv8-A and Armv8-M.|
67 | CMSIS/Core | CMSIS-Core(M) related files (for release) |
69 | CMSIS/CoreValidation | Validation for Core(M) and Core(A) (NOT part of release) |
74 | CMSIS/RTOS | RTOS v1 related files (for Cortex-M) |
[all …]
/bsp/msp432e401y-LaunchPad/libraries/Drivers/
A Ddrv_gpio.c99 _MSP432_PIN(65, M, 0),
100 _MSP432_PIN(66, M, 1),
101 _MSP432_PIN(67, M, 2),
102 _MSP432_PIN(68, M, 3),
103 _MSP432_PIN(69, M, 4),
104 _MSP432_PIN(70, M, 5),
105 _MSP432_PIN(71, M, 6),
106 _MSP432_PIN(72, M, 7),
/bsp/beaglebone/
A DAM335x_sk_DDR3.mac68 mpu_pll_config( clk_in, N, M, M2)
75 clk_out = (ref_clk*M)/M2;
92 clksel = clksel | ((M <<0x8) | N);
132 clksel = clksel | ((M <<0x8) | N);
151 ddr_pll_config( clk_in, N, M, M2)
157 clk_out = (ref_clk*M)/M2;
170 clksel = clksel | ((M <<0x8) | N);
189 clk_out = (ref_clk*M)/M2;
202 clksel = clksel | ((M <<0x8) | N);
222 clk_out = (ref_clk*M)/M2;
[all …]
/bsp/wh44b0/
A Dskyeye.conf3 mem_bank: map=M, type=R, addr=0x00000000, size=0x00200000, file=./rtthread-wh44b0.bin
5 mem_bank: map=M, type=RW, addr=0x0C000000, size=0x00800000
/bsp/qemu-vexpress-a9/
A Dqemu-nographic.bat3 qemu-img create -f raw sd.bin 64M
6 qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -nographic -sd sd.bin
A Dqemu-dbg.bat3 qemu-img create -f raw sd.bin 64M
6 qemu-system-arm -M vexpress-a9 -kernel rtthread.bin -serial stdio -sd sd.bin -S -s
A Dqemu.bat3 qemu-img create -f raw sd.bin 64M
7 qemu-system-arm -M vexpress-a9 -smp cpus=2 -kernel rtthread.bin -serial stdio -sd sd.bin
/bsp/raspberry-pi/raspi3-64/
A Dqemu-64.bat3 qemu-img create -f raw sd.bin 64M
6 qemu-system-aarch64 -M raspi3 -kernel kernel8.img -serial null -serial stdio -sd sd.bin
/bsp/simulator/
A Dreadme.md53 sd.bin--模拟SD卡，挂载fat，大小为16M
54 nand.bin-模拟nand flash，挂载uffs，参数page=2048+64bytes，block=64pages，16M
55 nor.bin--模拟nor flash，挂载jffs2，型号为sst25vf，2M
/bsp/mm32f526x/board/linker_scripts/
A Dlink.lds38 /* ARMv8-M stack sealing:
39 to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
79 * __StackSeal (only if ARMv8-M stack sealing is used)
212 /* ARMv8-M stack sealing:
213 to use ARMv8-M stack sealing uncomment '.stackseal' section
/bsp/mm32f526x/drivers/linker_scripts/
A Dlink.lds38 /* ARMv8-M stack sealing:
39 to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0
79 * __StackSeal (only if ARMv8-M stack sealing is used)
212 /* ARMv8-M stack sealing:
213 to use ARMv8-M stack sealing uncomment '.stackseal' section
/bsp/nxp/lpc/lpc408x/
A DREADME.md11 | 主频 | 120M |
13 | 片外 SDRAM | 32M |
/bsp/qemu-virt64-riscv/
A Dqemu-nographic.bat3 qemu-img create -f raw sd.bin 64M
6 qemu-system-riscv64 -nographic -machine virt -m 256M -kernel rtthread.bin ^
/bsp/rockchip/rk2108/
A Dgcc_xip_off.ld.S10 FLASH (rx) : ORIGIN = 0x18000000, LENGTH = 16M /* Nor Flash */
11 SRAM_I (rxw) : ORIGIN = 0x04000000, LENGTH = 1M /* SRAM */
12 SRAM_D (rxw) : ORIGIN = 0x20000000, LENGTH = 1M /* SRAM */
/bsp/qemu-virt64-aarch64/
A Dqemu.bat3 qemu-img create -f raw sd.bin 64M
6 qemu-system-aarch64 -M virt,gic-version=2 -cpu cortex-a53 -smp 4 -kernel rtthread.bin -nographic ^
/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/
A Dflash_sdram_uf2.icf27 define symbol __size_flash__ = 8M;
33 define symbol __size_exram__ = 256M;
43 define region SDRAM = mem:[from 0x40000000 size __size_exram__ - 32M];
44 define region NONCACHEABLE_RAM = mem:[from 0x40000000 + __size_exram__ - 32M size 32M];

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