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Searched refs:MASK (Results 1 – 25 of 149) sorted by relevance

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/bsp/CME_M7/StdPeriph_Driver/src/
A Dcmem7_can.c104 CANx->DI3_OR_AMR0 = f1->MASK.sf.ID28_18 >> 3; in can_SetFilter()
106 CANx->DI4_OR_AMR1 |= f1->MASK.sf.RTR << 4; in can_SetFilter()
107 CANx->DI5_OR_AMR2 = f1->MASK.sf.data1; in can_SetFilter()
108 CANx->DI6_OR_AMR3 = f1->MASK.sf.data2; in can_SetFilter()
116 CANx->DI3_OR_AMR0 = f1->MASK.sf.ID28_18 >> 3; in can_SetFilter()
118 CANx->DI4_OR_AMR1 |= f1->MASK.sf.RTR << 4; in can_SetFilter()
119 CANx->DI4_OR_AMR1 = f1->MASK.sf.data1 >> 4; in can_SetFilter()
120 CANx->DI6_OR_AMR3 = f1->MASK.sf.data1 & 0x0F; in can_SetFilter()
128 CANx->DI3_OR_AMR0 = f1->MASK.ef.ID28_13 >> 8; in can_SetFilter()
130 CANx->DI5_OR_AMR2 = f1->MASK.ef.ID12_0 >> 5; in can_SetFilter()
[all …]
/bsp/ft32/libraries/FT32F0xx/FT32F0xx_Driver/Inc/
A Dft32f0xx_rtc.h259 #define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) argument
312 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ argument
313 ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
314 ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
315 ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
316 ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
317 ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
318 ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
319 ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
326 ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
[all …]
A Dft32f0xx_i2c.h201 #define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \ argument
202 ((MASK) == I2C_OA2_Mask01) || \
203 ((MASK) == I2C_OA2_Mask02) || \
204 ((MASK) == I2C_OA2_Mask03) || \
205 ((MASK) == I2C_OA2_Mask04) || \
206 ((MASK) == I2C_OA2_Mask05) || \
207 ((MASK) == I2C_OA2_Mask06) || \
208 ((MASK) == I2C_OA2_Mask07))
/bsp/rockchip/common/rk_hal/lib/hal/inc/
A Dhal_def.h34 #define CLEAR_BIT(REG, MASK) ((*(volatile uint32_t *)&(REG)) &= ~(MASK)) /**< Clear the specif… argument
35 #define READ_BIT(REG, MASK) ((*(volatile const uint32_t *)&(REG)) & (MASK)) /**< Read the value o… argument
55 #define HAL_IS_BIT_SET(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) != RESET) /**< Check … argument
56 #define HAL_IS_BIT_CLR(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) == RESET) /**< Check … argument
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/inc/
A Dhk32f0xx_rtc.h257 #define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) argument
310 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ argument
311 ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
312 ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
313 ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
314 ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
315 ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
316 ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
317 ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
324 ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
[all …]
A Dhk32f0xx_i2c.h200 #define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \ argument
201 ((MASK) == I2C_OA2_Mask01) || \
202 ((MASK) == I2C_OA2_Mask02) || \
203 ((MASK) == I2C_OA2_Mask03) || \
204 ((MASK) == I2C_OA2_Mask04) || \
205 ((MASK) == I2C_OA2_Mask05) || \
206 ((MASK) == I2C_OA2_Mask06) || \
207 ((MASK) == I2C_OA2_Mask07))
/bsp/ht32/libraries/HT32_STD_1xxxx_FWLib/library/HT32F1xxxx_Driver/inc/
A Dht32f1xxxx_i2c.h242 #define IS_I2C_ADDRESS_MASK(MASK) ((MASK == I2C_MASKBIT_0) || \ argument
243 (MASK == I2C_MASKBIT_1) || \
244 (MASK == I2C_MASKBIT_2) || \
245 (MASK == I2C_MASKBIT_3) || \
246 (MASK == I2C_MASKBIT_4) || \
247 (MASK == I2C_MASKBIT_5) || \
248 (MASK == I2C_MASKBIT_6) || \
249 (MASK == I2C_MASKBIT_7) || \
250 (MASK == I2C_MASKBIT_8) || \
251 (MASK == I2C_MASKBIT_9))
/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_dwdma.c170 DW_CHAN_CLEAR_BIT(reg->MASK.TFR, dw->allChanMask); in DWDMA_off()
174 DW_CHAN_CLEAR_BIT(reg->MASK.ERR, dw->allChanMask); in DWDMA_off()
211 DW_CHAN_SET_BIT(dw->pReg->MASK.TFR, dwc->mask); in DWC_initialize()
212 DW_CHAN_SET_BIT(dw->pReg->MASK.ERR, dwc->mask); in DWC_initialize()
223 DW_CHAN_CLEAR_BIT(dw->pReg->MASK.TFR, dwc->mask); in DWC_deinitialize()
224 DW_CHAN_CLEAR_BIT(dw->pReg->MASK.ERR, dwc->mask); in DWC_deinitialize()
567 DW_CHAN_CLEAR_BIT(dw->pReg->MASK.TFR, dwc->mask); in HAL_DWDMA_IrqHandler()
569 DW_CHAN_CLEAR_BIT(dw->pReg->MASK.ERR, dwc->mask); in HAL_DWDMA_IrqHandler()
574 DW_CHAN_SET_BIT(dw->pReg->MASK.TFR, dwc->mask); in HAL_DWDMA_IrqHandler()
575 DW_CHAN_SET_BIT(dw->pReg->MASK.ERR, dwc->mask); in HAL_DWDMA_IrqHandler()
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/bsp/stm32/libraries/HAL_Drivers/drivers/
A Ddrv_usart_v2.h28 #define UART_GET_RDR(__HANDLE__, MASK) ((__HANDLE__)->Instance->RDR & MASK) argument
32 #define UART_GET_RDR(__HANDLE__, MASK) ((__HANDLE__)->Instance->DR & MASK) argument
/bsp/ht32/libraries/HT32_STD_5xxxx_FWLib/library/HT32F5xxxx_Driver/inc/
A Dht32f5xxxx_i2c.h300 #define IS_I2C_ADDRESS_MASK(MASK) ((MASK == I2C_MASKBIT_0) || \ argument
301 (MASK == I2C_MASKBIT_1) || \
302 (MASK == I2C_MASKBIT_2) || \
303 (MASK == I2C_MASKBIT_3) || \
304 (MASK == I2C_MASKBIT_4) || \
305 (MASK == I2C_MASKBIT_5) || \
306 (MASK == I2C_MASKBIT_6) || \
307 (MASK == I2C_MASKBIT_7) || \
308 (MASK == I2C_MASKBIT_8) || \
309 (MASK == I2C_MASKBIT_9))
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_hal_rtc_ex.h534 #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ argument
535 ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
536 ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
537 ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
538 ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
539 ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
540 ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
541 ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
542 ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
548 ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
[all …]
/bsp/apm32/libraries/APM32E10x_Library/APM32E10x_StdPeriphDriver/src/
A Dapm32e10x_sdio.c59 SDIO->MASK = 0x00000000; in SDIO_Reset()
557 SDIO->MASK |= interrupt; in SDIO_EnableInterrupt()
593 SDIO->MASK &= ~interrupt; in SDIO_DisableInterrupt()
706 intEnable = (uint32_t)(SDIO->MASK & flag); in SDIO_ReadIntFlag()
/bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/src/
A Dapm32f10x_sdio.c59 SDIO->MASK = 0x00000000; in SDIO_Reset()
553 SDIO->MASK |= interrupt; in SDIO_EnableInterrupt()
589 SDIO->MASK &= ~interrupt; in SDIO_DisableInterrupt()
692 intEnable = (uint32_t)(SDIO->MASK & flag); in SDIO_ReadIntFlag()
/bsp/rockchip/common/rk_hal/lib/hal/src/pinctrl/
A Dhal_pinctrl_iofunc.c58 #define _IOMUX_WRITE(REG, DATA, SHIFT, MASK) \ argument
60 HAL_ASSERT((uint32_t)((DATA) << (SHIFT)) <= (uint32_t)(MASK)); \
62 REG = ((DATA) << (SHIFT)) | ((MASK) << 16); \
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32G/Include/
A Defm32g880f128.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32g880f32.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32g880f64.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32g890f128.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32g890f32.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32g890f64.h398 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
399 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
/bsp/apm32/libraries/APM32F4xx_Library/APM32F4xx_StdPeriphDriver/src/
A Dapm32f4xx_sdio.c541 SDIO->MASK |= interrupt; in SDIO_EnableInterrupt()
578 SDIO->MASK &= ~interrupt; in SDIO_DisableInterrupt()
681 intEnable = (uint32_t)(SDIO->MASK & flag); in SDIO_ReadIntFlag()
/bsp/wch/arm/Libraries/CH32F20x_StdPeriph_Driver/StdPeriph_Driver/src/
A Dch32f20x_sdio.c45 SDIO->MASK = 0x00000000; in SDIO_DeInit()
164 SDIO->MASK |= SDIO_IT; in SDIO_ITConfig()
168 SDIO->MASK &= ~SDIO_IT; in SDIO_ITConfig()
/bsp/efm32/Libraries/Device/EnergyMicro/EFM32GG/Include/
A Defm32gg990f512.h457 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
458 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32gg995f1024.h457 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
458 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
A Defm32gg995f512.h457 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \ argument
458 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));

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