Searched refs:MCK (Results 1 – 10 of 10) sorted by relevance
22 #define MCK 48054857 macro24 #define BRD (MCK/16/BR) /* Baud Rate Divisor */
54 #define MCK 48054857 macro56 #define BRD (MCK/16/BR) /* Baud Rate Divisor */
30 #define PIV (((MCK/16)/1000)*(1000/RT_TICK_PER_SECOND))
159 bd = ((MCK*10)/(serial->baudrate * 16)); in rt_serial_init()
324 #define MCK 48054857 macro
16 #define MCK 50000000 macro
167 input: Master Clock (MCK)171 afec_clock_source: Master Clock (MCK)190 _$freq_output_Master Clock (MCK): 150000000207 clk_gen_gclk0_oscillator: Master Clock (MCK)275 mck_div_8_src: Master Clock (MCK)352 input: Master Clock (MCK)356 twihs_clock_source: Master Clock (MCK)404 input: Master Clock (MCK)408 usart_clock_source: Master Clock (MCK)794 input: Master Clock (MCK)[all …]
84 # Set core at 200 MHz and MCK at 100 MHz
119 // Set core at 200 MHz and MCK at 100 MHz
227 * Set core at 200 MHz and MCK at 100 MHz
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