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Searched refs:MCLK_APBCMASK_TC4_Pos (Results 1 – 8 of 8) sorted by relevance

/bsp/microchip/samc21/bsp/samc21/include/component/
A Dmclk.h330 #define MCLK_APBCMASK_TC4_Pos 16 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */ macro
331 #define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
/bsp/microchip/same54/bsp/include/component/
A Dmclk.h391 #define MCLK_APBCMASK_TC4_Pos 5 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */ macro
392 #define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dmclk.h381 #define MCLK_APBCMASK_TC4_Pos 5 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */ macro
382 #define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dmclk.h381 #define MCLK_APBCMASK_TC4_Pos 5 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */ macro
382 #define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
/bsp/microchip/samc21/bsp/hri/
A Dhri_mclk_c21.h2135 tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; in hri_mclk_get_APBCMASK_TC4_bit()
2145 tmp |= value << MCLK_APBCMASK_TC4_Pos; in hri_mclk_write_APBCMASK_TC4_bit()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_mclk_d51.h2480 tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; in hri_mclk_get_APBCMASK_TC4_bit()
2490 tmp |= value << MCLK_APBCMASK_TC4_Pos; in hri_mclk_write_APBCMASK_TC4_bit()
/bsp/microchip/same54/bsp/hri/
A Dhri_mclk_e54.h2640 tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; in hri_mclk_get_APBCMASK_TC4_bit()
2650 tmp |= value << MCLK_APBCMASK_TC4_Pos; in hri_mclk_write_APBCMASK_TC4_bit()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_mclk_d51.h2480 tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; in hri_mclk_get_APBCMASK_TC4_bit()
2490 tmp |= value << MCLK_APBCMASK_TC4_Pos; in hri_mclk_write_APBCMASK_TC4_bit()

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