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Searched refs:MCLK_APBCMASK_TCC2_Pos (Results 1 – 8 of 8) sorted by relevance

/bsp/microchip/samc21/bsp/samc21/include/component/
A Dmclk.h320 #define MCLK_APBCMASK_TCC2_Pos 11 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable … macro
321 #define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
/bsp/microchip/same54/bsp/include/component/
A Dmclk.h387 #define MCLK_APBCMASK_TCC2_Pos 3 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable … macro
388 #define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
/bsp/microchip/samd51-seeed-wio-terminal/bsp/samd51a/include/component/
A Dmclk.h377 #define MCLK_APBCMASK_TCC2_Pos 3 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable … macro
378 #define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
/bsp/microchip/samd51-adafruit-metro-m4/bsp/samd51a/include/component/
A Dmclk.h377 #define MCLK_APBCMASK_TCC2_Pos 3 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable … macro
378 #define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
/bsp/microchip/samc21/bsp/hri/
A Dhri_mclk_c21.h1935 tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; in hri_mclk_get_APBCMASK_TCC2_bit()
1945 tmp |= value << MCLK_APBCMASK_TCC2_Pos; in hri_mclk_write_APBCMASK_TCC2_bit()
/bsp/microchip/samd51-seeed-wio-terminal/bsp/hri/
A Dhri_mclk_d51.h2400 tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; in hri_mclk_get_APBCMASK_TCC2_bit()
2410 tmp |= value << MCLK_APBCMASK_TCC2_Pos; in hri_mclk_write_APBCMASK_TCC2_bit()
/bsp/microchip/same54/bsp/hri/
A Dhri_mclk_e54.h2560 tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; in hri_mclk_get_APBCMASK_TCC2_bit()
2570 tmp |= value << MCLK_APBCMASK_TCC2_Pos; in hri_mclk_write_APBCMASK_TCC2_bit()
/bsp/microchip/samd51-adafruit-metro-m4/bsp/hri/
A Dhri_mclk_d51.h2400 tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; in hri_mclk_get_APBCMASK_TCC2_bit()
2410 tmp |= value << MCLK_APBCMASK_TCC2_Pos; in hri_mclk_write_APBCMASK_TCC2_bit()

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