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Searched refs:MMCCLK (Results 1 – 3 of 3) sorted by relevance

/bsp/dm365/drivers/
A Dmmcsd.c163 temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; in calculate_clk_divider()
165 host->mmcsd_regs->MMCCLK = temp; in calculate_clk_divider()
178 temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKEN; in calculate_clk_divider()
179 host->mmcsd_regs->MMCCLK = temp; in calculate_clk_divider()
183 temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; in calculate_clk_divider()
185 host->mmcsd_regs->MMCCLK = temp; in calculate_clk_divider()
187 host->mmcsd_regs->MMCCLK = temp | MMCCLK_CLKEN; in calculate_clk_divider()
1104 host->mmcsd_regs->MMCCLK = 0; in init_mmcsd_host()
1105 host->mmcsd_regs->MMCCLK = MMCCLK_CLKEN; in init_mmcsd_host()
A Dmmcsd.h101 volatile rt_uint32_t MMCCLK; member
/bsp/mini4020/drivers/
A Dsdcard.h21 #define MMCCLK 15000000 //PCLK=49.392MHz macro

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