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Searched refs:MMC_SDIO1_PLL_REGISTER (Results 1 – 2 of 2) sorted by relevance

/bsp/cvitek/drivers/libraries/sdif/
A Ddw_sdmmc.h371 #define MMC_SDIO1_PLL_REGISTER (CLK_DIV_BASE + 0x7C) macro
/bsp/cvitek/drivers/
A Ddrv_sdhci.c794 mmio_write_32(MMC_SDIO1_PLL_REGISTER, MMC_MAX_CLOCK_DIV_VALUE); in rthw_sdhci_set_config()

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