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Searched refs:MM_MISC_BASE (Results 1 – 6 of 6) sorted by relevance

/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/
A Dbl808_glb.c2797 tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); in GLB_Set_DSP_MTimer_CLK()
2799 BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); in GLB_Set_DSP_MTimer_CLK()
2801 tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); in GLB_Set_DSP_MTimer_CLK()
2803 BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); in GLB_Set_DSP_MTimer_CLK()
2804 tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); in GLB_Set_DSP_MTimer_CLK()
2806 BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); in GLB_Set_DSP_MTimer_CLK()
2807 tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); in GLB_Set_DSP_MTimer_CLK()
2809 BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); in GLB_Set_DSP_MTimer_CLK()
2811 tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); in GLB_Set_DSP_MTimer_CLK()
2818 BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); in GLB_Set_DSP_MTimer_CLK()
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A Dbl808_clock.c1945 address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET; in CPU_Set_MTimer_RST()
2007 address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET; in CPU_Set_MTimer_CLK()
2102 address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET; in CPU_Get_MTimer_Clock()
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/
A Dbl616_memorymap.h93 #define MM_MISC_BASE ((uint32_t)0x20050000) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/
A Dbl808_memorymap.h107 #define MM_MISC_BASE ((uint32_t)0x30000000) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/
A Dbl616.h227 #define MM_MISC_BASE ((uint32_t)0x20050000) macro
/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/
A Dbl808.h451 #define MM_MISC_BASE ((uint32_t)0x30000000) macro

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