1 /* 2 * Copyright (C) 2018 ETH Zurich and University of Bologna 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /* 18 * Copyright (C) 2018 GreenWaves Technologies 19 * 20 * Licensed under the Apache License, Version 2.0 (the "License"); 21 * you may not use this file except in compliance with the License. 22 * You may obtain a copy of the License at 23 * 24 * http://www.apache.org/licenses/LICENSE-2.0 25 * 26 * Unless required by applicable law or agreed to in writing, software 27 * distributed under the License is distributed on an "AS IS" BASIS, 28 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 29 * See the License for the specific language governing permissions and 30 * limitations under the License. 31 */ 32 33 #ifndef __HIMAX_H__ 34 #define __HIMAX_H__ 35 36 /* 37 * HIMAX camera macros 38 */ 39 // Register address 40 // Read only registers 41 #define MODEL_ID_H 0x0000 42 #define MODEL_ID_L 0x0001 43 #define FRAME_COUNT 0x0005 44 #define PIXEL_ORDER 0x0006 45 // R&W registers 46 // Sensor mode control 47 #define MODE_SELECT 0x0100 48 #define IMG_ORIENTATION 0x0101 49 #define SW_RESET 0x0103 50 #define GRP_PARAM_HOLD 0x0104 51 // Sensor exposure gain control 52 #define INTEGRATION_H 0x0202 53 #define INTEGRATION_L 0x0203 54 #define ANALOG_GAIN 0x0205 55 #define DIGITAL_GAIN_H 0x020E 56 #define DIGITAL_GAIN_L 0x020F 57 // Frame timing control 58 #define FRAME_LEN_LINES_H 0x0340 59 #define FRAME_LEN_LINES_L 0x0341 60 #define LINE_LEN_PCK_H 0x0342 61 #define LINE_LEN_PCK_L 0x0343 62 // Binning mode control 63 #define READOUT_X 0x0383 64 #define READOUT_Y 0x0387 65 #define BINNING_MODE 0x0390 66 // Test pattern control 67 #define TEST_PATTERN_MODE 0x0601 68 // Black level control 69 #define BLC_CFG 0x1000 70 #define BLC_TGT 0x1003 71 #define BLI_EN 0x1006 72 #define BLC2_TGT 0x1007 73 // Sensor reserved 74 #define DPC_CTRL 0x1008 75 #define SINGLE_THR_HOT 0x100B 76 #define SINGLE_THR_COLD 0x100C 77 // VSYNC,HSYNC and pixel shift register 78 #define VSYNC_HSYNC_PIXEL_SHIFT_EN 0x1012 79 // Automatic exposure gain control 80 #define AE_CTRL 0x2100 81 #define AE_TARGET_MEAN 0x2101 82 #define AE_MIN_MEAN 0x2102 83 #define CONVERGE_IN_TH 0x2103 84 #define CONVERGE_OUT_TH 0x2104 85 #define MAX_INTG_H 0x2105 86 #define MAX_INTG_L 0x2106 87 #define MIN_INTG 0x2107 88 #define MAX_AGAIN_FULL 0x2108 89 #define MAX_AGAIN_BIN2 0x2109 90 #define MIN_AGAIN 0x210A 91 #define MAX_DGAIN 0x210B 92 #define MIN_DGAIN 0x210C 93 #define DAMPING_FACTOR 0x210D 94 #define FS_CTRL 0x210E 95 #define FS_60HZ_H 0x210F 96 #define FS_60HZ_L 0x2110 97 #define FS_50HZ_H 0x2111 98 #define FS_50HZ_L 0x2112 99 #define FS_HYST_TH 0x2113 100 // Motion detection control 101 #define MD_CTRL 0x2150 102 #define I2C_CLEAR 0x2153 103 #define WMEAN_DIFF_TH_H 0x2155 104 #define WMEAN_DIFF_TH_M 0x2156 105 #define WMEAN_DIFF_TH_L 0x2157 106 #define MD_THH 0x2158 107 #define MD_THM1 0x2159 108 #define MD_THM2 0x215A 109 #define MD_THL 0x215B 110 // Sensor timing control 111 #define QVGA_WIN_EN 0x3010 112 #define SIX_BIT_MODE_EN 0x3011 113 #define PMU_AUTOSLEEP_FRAMECNT 0x3020 114 #define ADVANCE_VSYNC 0x3022 115 #define ADVANCE_HSYNC 0x3023 116 #define EARLY_GAIN 0x3035 117 // IO and clock control 118 #define BIT_CONTROL 0x3059 119 #define OSC_CLK_DIV 0x3060 120 #define ANA_Register_11 0x3061 121 #define IO_DRIVE_STR 0x3062 122 #define IO_DRIVE_STR2 0x3063 123 #define ANA_Register_14 0x3064 124 #define OUTPUT_PIN_STATUS_CONTROL 0x3065 125 #define ANA_Register_17 0x3067 126 #define PCLK_POLARITY 0x3068 127 128 /* 129 * Useful value of Himax registers 130 */ 131 #define HIMAX_RESET 0x01 132 #define Pclk_rising_edge 0x00 133 #define Pclk_falling_edge 0x01 134 135 #define BYPASS_BIGEND 5 136 137 enum{ 138 HIMAX_Standby = 0x0, 139 HIMAX_Streaming = 0x1, // I2C triggered streaming enable 140 HIMAX_Streaming2 = 0x3, // Output N frames 141 HIMAX_Streaming3 = 0x5 // Hardware Trigger 142 }; 143 144 #endif 145