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Searched refs:MODIFY_REG (Results 1 – 25 of 253) sorted by relevance

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/bsp/mm32f327x/Libraries/MM32F327x/HAL_Lib/Src/
A Dhal_tim.c514 MODIFY_REG(tim->SMCR, TIM_SMCR_ETP, polarity); in TIM_ETRConfig()
515 MODIFY_REG(tim->SMCR, TIM_SMCR_ETPS, psc); in TIM_ETRConfig()
615 MODIFY_REG(tim->SMCR, TIM_SMCR_TS, source); in TIM_SelectInputTrigger()
1121 MODIFY_REG(tim->CR1, TIM_CR1_URS, source); in TIM_UpdateRequestConfig()
1147 MODIFY_REG(tim->CR1, TIM_CR1_OPM, mode); in TIM_SelectOnePulseMode()
1170 MODIFY_REG(tim->CR2, TIM_CR2_MMS, source); in TIM_SelectOutputTrigger()
1187 MODIFY_REG(tim->SMCR, TIM_SMCR_SMS, mode); in TIM_SelectSlaveMode()
1202 MODIFY_REG(tim->SMCR, TIM_SMCR_MSM, mode); in TIM_SelectMasterSlaveMode()
1229 MODIFY_REG(tim->CCMR1, TIM_CCMR1_IC1PSC, psc); in TIM_SetIC1Prescaler()
1261 MODIFY_REG(tim->CCMR2, TIM_CCMR2_IC3PSC, psc); in TIM_SetIC3Prescaler()
[all …]
A Dhal_uart.c88 MODIFY_REG(uart->CCR, UART_CCR_CHAR, init_struct->WordLength); in UART_Init()
97 MODIFY_REG(uart->GCR, UART_GCR_AUTOFLOW, init_struct->HWFlowControl); in UART_Init()
139 MODIFY_REG(uart->GCR, UART_GCR_UART, state << UART_GCR_UART_Pos); in UART_Cmd()
175 MODIFY_REG(uart->GCR, UART_GCR_DMA, state << UART_GCR_DMA_Pos); in UART_DMACmd()
261 MODIFY_REG(uart->CCR, UART_CCR_WAKE, mode); in UART_WakeUpConfig()
272 MODIFY_REG(uart->CCR, UART_CCR_RWU, state << UART_CCR_RWU_Pos); in UART_ReceiverWakeUpCmd()
283 MODIFY_REG(uart->RXAR, UART_RXAR_ADDR, address); in UART_SetRXAddress()
294 MODIFY_REG(uart->RXMR, UART_RXMR_MASK, address); in UART_SetRXMASK()
305 MODIFY_REG(uart->CCR, UART_CCR_B8EN, state << UART_CCR_B8EN_Pos); in UART_Enable9bit()
327 MODIFY_REG(uart->CCR, UART_CCR_B8POL, polarity); in UART_Set9bitPolarity()
[all …]
/bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/
A Dald_pis.c282 …MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS… in ald_pis_modu_config()
283 MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); in ald_pis_modu_config()
284 …MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POS… in ald_pis_modu_config()
288 …MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS… in ald_pis_modu_config()
289 MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); in ald_pis_modu_config()
290 …MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POS… in ald_pis_modu_config()
294 …MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS… in ald_pis_modu_config()
295 MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); in ald_pis_modu_config()
300 …MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS… in ald_pis_modu_config()
301 MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS); in ald_pis_modu_config()
[all …]
A Dald_timer.c2807 MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); in ald_timer_com_change_config()
2808 MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); in ald_timer_com_change_config()
2809 MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); in ald_timer_com_change_config()
2810 MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); in ald_timer_com_change_config()
2811 MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); in ald_timer_com_change_config()
2812 MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); in ald_timer_com_change_config()
2813 MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); in ald_timer_com_change_config()
2814 MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); in ald_timer_com_change_config()
2815 MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); in ald_timer_com_change_config()
2900 MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); in ald_timer_break_dead_time_config()
[all …]
A Dald_cmu.c410 MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); in ald_cmu_clock_config()
500 MODIFY_REG(tmp, CMU_HRCACR_AC_MSK, 1 << CMU_HRCACR_AC_POSS); in ald_cmu_auto_calib_clock()
501 MODIFY_REG(tmp, CMU_HRCACR_RFSEL_MSK, input << CMU_HRCACR_RFSEL_POS); in ald_cmu_auto_calib_clock()
502 MODIFY_REG(tmp, CMU_HRCACR_FREQ_MSK, freq << CMU_HRCACR_FREQ_POS); in ald_cmu_auto_calib_clock()
563 MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); in ald_cmu_div_config()
567 MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); in ald_cmu_div_config()
580 MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); in ald_cmu_div_config()
736 MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); in ald_cmu_pll_safe_config()
929 MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); in ald_cmu_buzz_config()
930 MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); in ald_cmu_buzz_config()
[all …]
A Dald_rtc.c263 MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); in ald_rtc_init()
264 MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); in ald_rtc_init()
284 MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS); in ald_rtc_source_select()
714 MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS); in ald_rtc_set_time_stamp()
715 MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS); in ald_rtc_set_time_stamp()
879 MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS); in ald_rtc_set_wakeup()
952 MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS); in ald_rtc_set_clock_output()
1040 MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS); in ald_rtc_alarm_cmd()
1042 MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS); in ald_rtc_alarm_cmd()
1063 MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); in ald_rtc_set_shift()
[all …]
/bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Source/
A Dald_pis.c275 …MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK, config->level << PIS_UART0_TXMCR… in ald_pis_modu_config()
276 …MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, config->src << PIS_UART0_TXMCR_TXM… in ald_pis_modu_config()
277 …MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, config->channel << PIS_UART0_TXMC… in ald_pis_modu_config()
281 …MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK, config->level << PIS_UART1_TXMCR… in ald_pis_modu_config()
282 …MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, config->src << PIS_UART1_TXMCR_TXM… in ald_pis_modu_config()
283 …MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, config->channel << PIS_UART1_TXMC… in ald_pis_modu_config()
287 …MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK, config->level << PIS_UART2_TXMCR… in ald_pis_modu_config()
288 …MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, config->src << PIS_UART2_TXMCR_TXM… in ald_pis_modu_config()
289 …MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, config->channel << PIS_UART2_TXMC… in ald_pis_modu_config()
293 …MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK, config->level << PIS_UART3_TXMCR… in ald_pis_modu_config()
[all …]
A Dald_timer.c2814 MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); in ald_timer_com_change_config()
2815 MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); in ald_timer_com_change_config()
2816 MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); in ald_timer_com_change_config()
2817 MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); in ald_timer_com_change_config()
2818 MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); in ald_timer_com_change_config()
2819 MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); in ald_timer_com_change_config()
2820 MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); in ald_timer_com_change_config()
2821 MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); in ald_timer_com_change_config()
2822 MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); in ald_timer_com_change_config()
2907 MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); in ald_timer_break_dead_time_config()
[all …]
A Dald_cmu.c401 MODIFY_REG(CMU->CSR, CMU_CSR_CFT_CMD_MSK, 0xAA << CMU_CSR_CFT_CMD_POSS); in ald_cmu_clock_config()
446 MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1); in ald_cmu_clock_config()
509 MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 0x3 << CMU_PULMCR_MODE_POSS); in ald_cmu_pll1_config()
565 MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS); in ald_cmu_div_config()
569 MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK2DIV_MSK, div << CMU_CFGR_HCLK2DIV_POSS); in ald_cmu_div_config()
573 MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); in ald_cmu_div_config()
586 MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS); in ald_cmu_div_config()
754 MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); in ald_cmu_pll_safe_config()
947 MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); in ald_cmu_buzz_config()
948 MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS); in ald_cmu_buzz_config()
[all …]
A Dald_pmu.c103 MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS); in ald_pmu_stop1_enter()
104 MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP1 << PMU_CR0_LPM_POSS); in ald_pmu_stop1_enter()
131 MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS); in ald_pmu_stop2_enter()
132 MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP2 << PMU_CR0_LPM_POSS); in ald_pmu_stop2_enter()
156 MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STANDBY << PMU_CR0_LPM_POSS); in ald_pmu_standby_enter()
198 MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, mode << PMU_CR1_LDO18MOD_POSS); in ald_pmu_ldo_18_config()
222 MODIFY_REG(PMU->CR0, PMU_CR0_LPVS_MSK, vol << PMU_CR0_LPVS_POSS); in ald_pmu_lprun_config()
325 MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); in ald_pmu_lvd_config()
326 MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS); in ald_pmu_lvd_config()
A Dald_rtc.c263 MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS); in ald_rtc_init()
264 MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS); in ald_rtc_init()
284 MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS); in ald_rtc_source_select()
714 MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS); in ald_rtc_set_time_stamp()
715 MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS); in ald_rtc_set_time_stamp()
879 MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS); in ald_rtc_set_wakeup()
952 MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS); in ald_rtc_set_clock_output()
1040 MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS); in ald_rtc_alarm_cmd()
1042 MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS); in ald_rtc_alarm_cmd()
1063 MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS); in ald_rtc_set_shift()
[all …]
A Dald_qspi.c422 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr); in ald_qspi_indac_transmit_by_it()
423 MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size); in ald_qspi_indac_transmit_by_it()
454 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr); in ald_qspi_indac_transmit_by_poll()
455 MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size); in ald_qspi_indac_transmit_by_poll()
515 MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr); in ald_qspi_indac_read_by_poll()
516 MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size); in ald_qspi_indac_read_by_poll()
587 MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size); in ald_qspi_indac_read_by_it()
714 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, addr); in ald_qspi_indac_transmit_by_dma()
715 MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size); in ald_qspi_indac_transmit_by_dma()
769 MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, addr); in ald_qspi_indac_read_by_dma()
[all …]
/bsp/essemi/es32vf2264/libraries/ALD/ES32VF2264/Source/
A Dald_pis.c269 …MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK, config->level << PIS_UART0_TXMCR… in ald_pis_modu_config()
270 …MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, config->src << PIS_UART0_TXMCR_TXM… in ald_pis_modu_config()
271 …MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, config->channel << PIS_UART0_TXMC… in ald_pis_modu_config()
275 …MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK, config->level << PIS_UART1_TXMCR… in ald_pis_modu_config()
276 …MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, config->src << PIS_UART1_TXMCR_TXM… in ald_pis_modu_config()
281 …MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK, config->level << PIS_UART2_TXMCR… in ald_pis_modu_config()
282 …MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, config->src << PIS_UART2_TXMCR_TXM… in ald_pis_modu_config()
287 …MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK, config->level << PIS_UART3_TXMCR… in ald_pis_modu_config()
288 …MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, config->src << PIS_UART3_TXMCR_TXM… in ald_pis_modu_config()
293 …MODIFY_REG(hperh->perh->UART4_TXMCR, PIS_UART4_TXMCR_TXMLVLS_MSK, config->level << PIS_UART4_TXMCR… in ald_pis_modu_config()
[all …]
A Dald_timer.c2799 MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4)); in ald_timer_com_change_config()
2800 MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12)); in ald_timer_com_change_config()
2801 MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4)); in ald_timer_com_change_config()
2802 MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0)); in ald_timer_com_change_config()
2803 MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2)); in ald_timer_com_change_config()
2804 MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4)); in ald_timer_com_change_config()
2805 MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6)); in ald_timer_com_change_config()
2806 MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8)); in ald_timer_com_change_config()
2807 MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10)); in ald_timer_com_change_config()
2892 MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS); in ald_timer_break_dead_time_config()
[all …]
A Dald_cmu.c298 MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 4000000 - 1); in ald_cmu_clock_config()
435 MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, 0); in ald_cmu_pll_config()
439 MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, 1); in ald_cmu_pll_config()
445 MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, 3); in ald_cmu_pll_config()
454 MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_REFS_MSK, input << CMU_PLLCFG_REFS_POSS); in ald_cmu_pll_config()
455 MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_CLKOS_MSK, output << CMU_PLLCFG_CLKOS_POSS); in ald_cmu_pll_config()
458 MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 0x2 << CMU_PULMCR_MODE_POSS); in ald_cmu_pll_config()
495 MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS); in ald_cmu_div_config()
603 MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS); in ald_cmu_pll_safe_config()
788 MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS); in ald_cmu_buzz_config()
[all …]
A Dald_pmu.c127 MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, ALD_PMU_LP_STOP << PMU_CR_LPM_POSS); in ald_pmu_stop_enter()
129 MODIFY_REG(PMU->CR, PMU_CR_LPSTOP_MSK | PMU_CR_BGSTOP_MSK | \ in ald_pmu_stop_enter()
134 MODIFY_REG(PMU->CR, PMU_CR_WKEVNSEL_MSK, (0x10 << PMU_CR_WKEVNSEL_POSS)); in ald_pmu_stop_enter()
149 MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, ALD_PMU_LP_STOP << PMU_CR_LPM_POSS); in ald_pmu_sleep_enter()
151 MODIFY_REG(PMU->CR, PMU_CR_WKEVNSEL_MSK, (0x10 << PMU_CR_WKEVNSEL_POSS)); in ald_pmu_sleep_enter()
189 MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS); in ald_pmu_lvd_config()
190 MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDIFS_MSK, mode << PMU_LVDCR_LVDIFS_POSS); in ald_pmu_lvd_config()
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/src/
A Dtae32f53xx_ll_gpio.c95 MODIFY_REG(GPIOx->PMUXR[position >> 3U], 0x0FU << ((position & 0x07U) * 4U), in LL_GPIO_Init()
99 … MODIFY_REG(GPIOx->OTYPR, 0x01U << position, (GPIO_Init->OType & 0x01U) << position); in LL_GPIO_Init()
102 … MODIFY_REG(GPIOx->OSRR, 0x01U << position, (GPIO_Init->Speed & 0x01U) << position); in LL_GPIO_Init()
108 MODIFY_REG(GPIOx->PMUXR[position >> 3U], 0x0FU << ((position & 0x07U) * 4U), in LL_GPIO_Init()
112 … MODIFY_REG(GPIOx->ITER, 0x01U << position, ((GPIO_Init->Mode >> 28U) & 0x01U) << position); in LL_GPIO_Init()
115 … MODIFY_REG(GPIOx->RFTSR, 0x01U << position, ((GPIO_Init->Mode >> 20U) & 0x01U) << position); in LL_GPIO_Init()
129 MODIFY_REG(GPIOx->PMUXR[position >> 3U], 0x0FU << ((position & 0x07U) * 4U), in LL_GPIO_Init()
133 … MODIFY_REG(GPIOx->OTYPR, 0x01U << position, (GPIO_Init->OType & 0x01U) << position); in LL_GPIO_Init()
136 … MODIFY_REG(GPIOx->OSRR, 0x01U << position, (GPIO_Init->Speed & 0x01U) << position); in LL_GPIO_Init()
189 MODIFY_REG(GPIOx->PMUXR[position >> 3U], (0x0FU << ((uint32_t)(position & 0x07U) * 4U)), in LL_GPIO_DeInit()
[all …]
A Dtae32f53xx_ll_ecu.c96 MODIFY_REG(Instance->CON, in LL_ECU_Init()
105 MODIFY_REG(Instance->PRC, in LL_ECU_Init()
115 MODIFY_REG(Instance->V_ADDR1, ECU_V_ADDR1_STADDR, ECU_Init->VStartAddr); in LL_ECU_Init()
117 MODIFY_REG(Instance->V_ADDR2, ECU_V_ADDR2_OFADDR, ECU_Init->VOffsetAddr); in LL_ECU_Init()
119 MODIFY_REG(Instance->I_ADDR1, ECU_I_ADDR1_STADDR, ECU_Init->IStartAddr); in LL_ECU_Init()
121 MODIFY_REG(Instance->I_ADDR2, ECU_I_ADDR2_OFADDR, ECU_Init->IOffsetAddr); in LL_ECU_Init()
142 MODIFY_REG(Instance->CON, in LL_ECU_DeInit()
225 MODIFY_REG(Instance->SQRT_IN, ECU_SQRT_INDATA, SqrtValue); in LL_ECU_WriteSqrtInData()
/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/
A DHAL_TIMER_EX.c24 MODIFY_REG(break_deadtime_reg, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); in HAL_TIMEx_ConfigBreakDeadTime()
25 MODIFY_REG(break_deadtime_reg, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); in HAL_TIMEx_ConfigBreakDeadTime()
26 MODIFY_REG(break_deadtime_reg, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); in HAL_TIMEx_ConfigBreakDeadTime()
27 MODIFY_REG(break_deadtime_reg, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); in HAL_TIMEx_ConfigBreakDeadTime()
28 MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); in HAL_TIMEx_ConfigBreakDeadTime()
29 MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); in HAL_TIMEx_ConfigBreakDeadTime()
30 MODIFY_REG(break_deadtime_reg, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); in HAL_TIMEx_ConfigBreakDeadTime()
31 …MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Po… in HAL_TIMEx_ConfigBreakDeadTime()
/bsp/fm33lc026/libraries/FM33LC0xx_FL_Driver/Inc/
A Dfm33lc0xx_fl_gptim.h621 MODIFY_REG(TIMx->CR1, GPTIM_CR1_CKD_Msk, div); in FL_GPTIM_SetClockDivision()
684 MODIFY_REG(TIMx->CR1, GPTIM_CR1_CMS_Msk, mode); in FL_GPTIM_SetCounterAlignedMode()
713 MODIFY_REG(TIMx->CR1, GPTIM_CR1_DIR_Msk, dir); in FL_GPTIM_SetCounterDirection()
740 MODIFY_REG(TIMx->CR1, GPTIM_CR1_OPM_Msk, mode); in FL_GPTIM_SetOnePulseMode()
767 MODIFY_REG(TIMx->CR1, GPTIM_CR1_URS_Msk, source); in FL_GPTIM_SetUpdateSource()
932 MODIFY_REG(TIMx->CR2, GPTIM_CR2_CCDS_Msk, trigger); in FL_GPTIM_CC_SetDMAReqTrigger()
1021 MODIFY_REG(TIMx->SMCR, GPTIM_SMCR_ETPS_Msk, psc); in FL_GPTIM_SetETRPrescaler()
1064 MODIFY_REG(TIMx->SMCR, GPTIM_SMCR_ETF_Msk, filter); in FL_GPTIM_SetETRFilter()
1741 MODIFY_REG(TIMx->PSC, (0xffffU << 0U), (psc << 0U)); in FL_GPTIM_WritePrescaler()
1897 MODIFY_REG(TIMx->DCR, GPTIM_DCR_DBL_Msk, length); in FL_GPTIM_SetDMABurstLength()
[all …]
/bsp/tae32f5300/Libraries/TAE32F53xx_StdPeriph_Driver/inc/
A Dtae32f53xx_ll_dma.h266 #define __LL_DMA_SrcPeriphBus_Set(__DMA__, ch, bus) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_…
275 #define __LL_DMA_DstPeriphBus_Set(__DMA__, ch, bus) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_…
284 #define __LL_DMA_TransType_Set(__DMA__, ch, type) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_…
293 #define __LL_DMA_SrcBurstLen_Set(__DMA__, ch, len) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_…
302 #define __LL_DMA_DstBurstLen_Set(__DMA__, ch, len) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_…
311 #define __LL_DMA_SrcAddrMode_Set(__DMA__, ch, mode) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_…
320 #define __LL_DMA_DstAddrMode_Set(__DMA__, ch, mode) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_…
329 #define __LL_DMA_SrcTransWidth_Set(__DMA__, ch, width) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_…
348 #define __LL_DMA_DstTransWidth_Set(__DMA__, ch, width) MODIFY_REG((__DMA__)->CH[(ch)].CR0, DMA_CH_…
401 …MODIFY_REG((__DMA__)->CH[(ch)].CR1, DMA_CH_CR1_BTCNT_Msk, (((cnt) & 0xfffUL) << DMA_CH_CR1_BTCNT_P…
[all …]
A Dtae32f53xx_ll_sysctrl.h93 MODIFY_REG((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_BAND_Msk, band)
102 MODIFY_REG((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_GVCO_Msk, vco)
134 MODIFY_REG((__SYSCTRL__)->PLL0CR, SYSCTRL_PLL0_REFCLK_Msk, ref_clk)
181 MODIFY_REG((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_BAND_Msk, band)
190 MODIFY_REG((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_GVCO_Msk, vco)
222 MODIFY_REG((__SYSCTRL__)->PLL1CR, SYSCTRL_PLL1_REFCLK_Msk, ref_clk)
269 MODIFY_REG((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_BAND_Msk, band)
278 MODIFY_REG((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_GVCO_Msk, vco)
310 MODIFY_REG((__SYSCTRL__)->PLL2CR, SYSCTRL_PLL2_REFCLK_Msk, ref_clk)
329 MODIFY_REG((__SYSCTRL__)->SCLKCR, SYSCTRL_SYSCLK_SRC_Msk, src)
[all …]
A Dtae32f53xx_ll_adc.h1160 MODIFY_REG((__INSTANCE__)->OFR[__OFFSETY__], ADC_OFR0_OFFSET, (__VALUE__))
1193 MODIFY_REG((__INSTANCE__)->GCR[(__GAINY__)], ADC_GCR0_GAIN, (__VALUE__))
1264 MODIFY_REG((__INSTANCE__)->DGCR[(__DGAINY__)], ADC_DGCR0_GAIN, (__VALUE__))
1318 MODIFY_REG((__INSTANCE__)->LR, ADC_LR_EXTEN | ADC_LR_EXTSEL, (__TRIGSRC__))
1428 MODIFY_REG((__INSTANCE__)->LR, ADC_LR_LEN, (__SEQUENCERANKS__))
1714 MODIFY_REG((__INSTANCE__)->DMA_CR[__CHANNLE__].TAR, ADC_DMA_TAR_ADDR, (__ADDR__))
1869 MODIFY_REG((__INSTANCE__)->JLR, ADC_JLR_JEXTEN, (__TRIG_EDGE__))
1897 MODIFY_REG((__INSTANCE__)->JLR, ADC_JLR_JLEN, (__SEQUENCERANK__))
1925 MODIFY_REG((__INSTANCE__)->CR1, ADC_CR1_JDISCEN, (__SEQDISCONT__))
2239 MODIFY_REG((__INSTANCE__)->AWDCR[__AWDY__], ADC_AWD0CR_AWD0CH, __AWDCHANNEL__)
[all …]
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_ll_tim.c527 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); in OC1Config()
533 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
645 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); in OC3Config()
749 MODIFY_REG(TIMx->CCMR1, in IC1Config()
754 MODIFY_REG(TIMx->CCER, in IC1Config()
782 MODIFY_REG(TIMx->CCMR1, in IC2Config()
787 MODIFY_REG(TIMx->CCER, in IC2Config()
815 MODIFY_REG(TIMx->CCMR2, in IC3Config()
820 MODIFY_REG(TIMx->CCER, in IC3Config()
848 MODIFY_REG(TIMx->CCMR2, in IC4Config()
[all …]
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_rtc.h799 MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); in LL_RTC_SetHourFormat()
915 MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); in LL_RTC_SetOutputPolarity()
1083 MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); in LL_RTC_TIME_SetFormat()
1116 MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), in LL_RTC_TIME_SetHour()
1186 MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), in LL_RTC_TIME_SetSecond()
1386 MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), in LL_RTC_DATE_SetYear()
1467 MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), in LL_RTC_DATE_SetMonth()
1509 MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), in LL_RTC_DATE_SetDay()
2383 MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); in LL_RTC_TS_SetActiveEdge()
2887 MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); in LL_RTC_WAKEUP_SetAutoReload()
[all …]

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