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Searched refs:MPU_RASR_B_Pos (Results 1 – 25 of 358) sorted by relevance

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/bsp/efm32/Libraries/emlib/src/
A Dem_mpu.c108 ((init->bufferable ? 1 : 0) << MPU_RASR_B_Pos) | in MPU_ConfigureRegion()
/bsp/synwit/libraries/SWM320_CSL/CMSIS/CoreSupport/
A Dcore_cm0plus.h572 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
573 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/efm32/Libraries/CMSIS/Include/
A Dcore_cm0plus.h528 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
529 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/ft32/libraries/FT32F0xx/CMSIS/FT32F0xx/Include/
A Dcore_cm0plus.h563 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
564 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/fujitsu/mb9x/mb9bf618s/CMSIS/Include/
A Dcore_sc000.h562 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
563 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
A Dcore_cm0plus.h543 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/CME_M7/CMSIS/CMSIS/Include/
A Dcore_sc000.h562 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
563 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
A Dcore_cm0plus.h543 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/mm32l07x/Libraries/CMSIS/CORE/
A Dcore_cm0plus.h543 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
A Dcore_sc000.h562 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
563 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/mm32l3xx/Libraries/CMSIS/IAR_CORE/
A Dcore_cm0plus.h572 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
573 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/mm32l07x/Libraries/CMSIS/IAR_CORE/
A Dcore_cm0plus.h572 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
573 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/mm32l3xx/Libraries/CMSIS/KEIL_CORE/
A Dcore_cm0plus.h543 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
A Dcore_sc000.h562 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
563 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/hk32/libraries/HK32F0xx_StdPeriph_Driver/CMSIS/Core/
A Dcore_cm0plus.h543 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
A Dcore_sc000.h562 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
563 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/nxp/lpc/lpc43xx/Libraries/CMSIS/Include/
A Dcore_cm0plus.h543 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
A Dcore_sc000.h562 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
563 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/mm32f103x/Libraries/CMSIS/KEIL_CORE/
A Dcore_sc000.h549 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
550 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
A Dcore_cm0plus.h531 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
532 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/mm32f103x/Libraries/CMSIS/IAR_CORE/
A Dcore_cm0plus.h560 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
561 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/nv32f100x/lib/inc/
A Dcore_cm0plus.h572 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
573 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/xplorer4330/Libraries/CMSIS/Include/
A Dcore_sc000.h562 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
563 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
A Dcore_cm0plus.h543 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …
/bsp/samd21/sam_d2x_asflib/CMSIS/Include/
A Dcore_cm0plus.h572 #define MPU_RASR_B_Pos 16 /*!< MPU … macro
573 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU …

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